EPM9560ARC240-10 vs EPM9560ARI240-10N 对比

详细并排对比 EPM9560ARC240-10 出自 Altera 和 EPM9560ARI240-10N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARC240-10 EPM9560ARI240-10N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $28.80 $105.00
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) —
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX) - 3rd generation
Usable Gates 12,000 12,000
Macrocells 560 560
User I/Os (this package) 191 (per Mouser listing) —
Internal Frequency 144.9 MHz —
Propagation Delay (tpd) 11.4 ns —
Supply Voltage - Internal (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) —
Process Technology CMOS EEPROM —
封装 240-pin PowerQuad QFP (RQFP / EAR240) 240-pin RQFP (RQFP-240 / PQFP-240)
工作温度 0C to +70C (commercial) -40C to +85C (industrial)
Configuration Memory EEPROM (non-volatile, in-system programmable) —
Logic Family CMOS CMOS, EEPROM-based
RoHS 状态 [DATA_NEEDED: RoHS status] —
Product Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 16
User I/Os — 216 (per digchip); 191 (per Mouser)
Maximum Internal Frequency — 144.9 MHz (typical); 145 MHz (per digchip)
Propagation Delay (tPD) — 10 ns (-10 speed grade)
电源电压 — 5.0 V nominal (4.5 V min, 5.5 V max)
In-System Programmability — Yes (5.0 V ISP via JTAG)
安装类型 — Surface Mount
JTAG (IEEE 1149.1) — Yes
Lead-Free / RoHS — [DATA_NEEDED: lead-free / RoHS status not in provided data]

数据手册与资源

浏览全部产品 创建 BOM 获取报价