EPM9560ARI240-10N vs EPM9560RC240-12 对比

详细并排对比 EPM9560ARI240-10N 出自 Intel 和 EPM9560RC240-12 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARI240-10N EPM9560RC240-12
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $105.00 $9.95
Family MAX 9000 MAX 9000 (EPM9560)
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 12,000 —
Macrocells 560 560
Logic Array Blocks (LABs) 16 20
User I/Os 216 (per digchip); 191 (per Mouser) —
Maximum Internal Frequency 144.9 MHz (typical); 145 MHz (per digchip) —
Propagation Delay (tPD) 10 ns (-10 speed grade) —
电源电压 5.0 V nominal (4.5 V min, 5.5 V max) —
Logic Family CMOS, EEPROM-based —
In-System Programmability Yes (5.0 V ISP via JTAG) —
封装 240-pin RQFP (RQFP-240 / PQFP-240) PQFP-240 (RC240) 0.500 mm pitch, gull-wing
安装类型 Surface Mount Surface Mount
工作温度 -40C to +85C (industrial) [DATA_NEEDED: operating temperature grade]
Architecture Multiple Array MatriX (MAX) - 3rd generation —
JTAG (IEEE 1149.1) Yes —
Lead-Free / RoHS [DATA_NEEDED: lead-free / RoHS status not in provided data] —
Device Type — EE PLD / CPLD
Flip-Flops — 772
User I/O Pins — 191
Maximum Propagation Delay (tPD) — 13.4 ns
Speed Grade — -12 (13.4 ns tPD)
Maximum Operating Frequency (estimated) — ~76 MHz registered
Core Supply Voltage (VCCINT) — 5 V
I/O Logic Levels — 3.3 V or 5 V (configurable)
Configuration Memory — EEPROM (non-volatile)
Programming Interface — IEEE 1149.1 JTAG
Process Technology — CMOS
RoHS 状态 — [DATA_NEEDED: RoHS compliance]

数据手册与资源

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