EPM9560ARI240-10N vs EPM9560RC240-1O 对比

详细并排对比 EPM9560ARI240-10N 出自 Intel 和 EPM9560RC240-1O 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARI240-10N EPM9560RC240-1O
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 最后采购期
库存状态 有库存 有库存
单价(USD) $105.00 $51.07
Family MAX 9000 MAX 9000
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 12,000 12,000
Macrocells 560 560
Logic Array Blocks (LABs) 16 35
User I/Os 216 (per digchip); 191 (per Mouser) —
Maximum Internal Frequency 144.9 MHz (typical); 145 MHz (per digchip) —
Propagation Delay (tPD) 10 ns (-10 speed grade) 12 ns (typ, -1 speed grade)
电源电压 5.0 V nominal (4.5 V min, 5.5 V max) —
Logic Family CMOS, EEPROM-based —
In-System Programmability Yes (5.0 V ISP via JTAG) —
封装 240-pin RQFP (RQFP-240 / PQFP-240) RQFP-240 (240-pin Reduced-height QFP)
安装类型 Surface Mount Surface Mount
工作温度 -40C to +85C (industrial) —
Architecture Multiple Array MatriX (MAX) - 3rd generation Multiple Array MatriX (MAX), third generation
JTAG (IEEE 1149.1) Yes —
Lead-Free / RoHS [DATA_NEEDED: lead-free / RoHS status not in provided data] —
Maximum User I/O Pins — 216
Global Setup Time (tFSU) — 3.0 ns
Clock-to-Output (tFCO) — 4.8 ns
Maximum Internal Frequency (fCNT) — 145 MHz
Supply Voltage (VCC) — 5.0 V
Operating Temperature (Grade) — -40C to +85C (industrial, "-1O" suffix)
Process Technology — CMOS EEPROM, 0.65 um
Programming — In-system programmable via IEEE 1149.1 JTAG
RoHS 状态 — Compliant (per Altera/Intel product page)
Lead-Free — Yes

数据手册与资源

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