EPM9560GC280-15 vs EPM9560ARI240-10N 对比

详细并排对比 EPM9560GC280-15 出自 Altera 和 EPM9560ARI240-10N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560GC280-15 EPM9560ARI240-10N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $115.00 $105.00
Family MAX 9000 MAX 9000
Device Type EE PLD (CMOS EEPROM-based CPLD) —
Macro Cells 560 —
Typical Gates 12,000 —
Maximum Operating Frequency 117.6 MHz —
Propagation Delay (tpd) 15 ns (speed grade -15) —
Propagation Delay (alternate datasheet figure) 16.6 ns —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Operating Temperature (Commercial) 0C to +70C —
Package Type CPGA-280 (Ceramic Pin Grid Array, 280 pins) —
安装类型 Through-Hole Surface Mount
Programmability In-System Programmable (ISP) via JTAG IEEE 1149.1 —
Technology CMOS EEPROM, 0.5 um process (MAX third-gen) —
Architecture Multiple Array MatriX (MAX) Multiple Array MatriX (MAX) - 3rd generation
RoHS 状态 Non-compliant (ceramic CPGA, contains lead) —
生命周期状态 Obsolete (legacy Altera MAX 9000 family) —
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 12,000
Macrocells — 560
Logic Array Blocks (LABs) — 16
User I/Os — 216 (per digchip); 191 (per Mouser)
Maximum Internal Frequency — 144.9 MHz (typical); 145 MHz (per digchip)
Propagation Delay (tPD) — 10 ns (-10 speed grade)
电源电压 — 5.0 V nominal (4.5 V min, 5.5 V max)
Logic Family — CMOS, EEPROM-based
In-System Programmability — Yes (5.0 V ISP via JTAG)
封装 — 240-pin RQFP (RQFP-240 / PQFP-240)
工作温度 — -40C to +85C (industrial)
JTAG (IEEE 1149.1) — Yes
Lead-Free / RoHS — [DATA_NEEDED: lead-free / RoHS status not in provided data]

数据手册与资源

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