EPM9560GC280-15N vs EPM9560GC280-15 对比
详细并排对比 EPM9560GC280-15N 出自 Intel 和 EPM9560GC280-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 Obsolete规格对比
| 参数 | EPM9560GC280-15N | EPM9560GC280-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $125.00 | $115.00 |
| Device Family | MAX 9000 | — |
| Product Type | EE PLD / CPLD | — |
| Macrocell Count | 560 | — |
| Usable Gates | 12,000 (typical) | — |
| Propagation Delay (tPD) | 16.6 ns | — |
| 最大时钟频率 | 117.6 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | 5.0 V |
| Maximum Supply Voltage | 5.25 V | — |
| Logic Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | — |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | — |
| 封装 | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | — |
| Package Code | PGA / CPGA280 | — |
| Terminal Form | PIN/PEG | — |
| Operating Temperature Grade | Commercial | — |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | Multiple Array MatriX (MAX) |
| Family | — | MAX 9000 |
| Device Type | — | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| 安装类型 | — | Through-Hole |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| RoHS 状态 | — | Non-compliant (ceramic CPGA, contains lead) |
| 生命周期状态 | — | Obsolete (legacy Altera MAX 9000 family) |