EPM9560GI280-20 vs EPM9560GC280-20 对比

详细并排对比 EPM9560GI280-20 出自 Intel 和 EPM9560GC280-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560GI280-20 EPM9560GC280-20
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $162.50 $360.00
Device Family MAX 9000 —
Architecture CMOS EEPROM-based Multiple Array MatriX (MAX) —
Technology Node 5.0 V CMOS EEPROM —
Macrocells 560 560
Logic Array Blocks (LABs) 28 (16 macrocells each) —
Usable Gates 12,000 12,000
Maximum User I/O Pins 216 —
Flip-Flops 772 —
Pin-to-Pin Delay (Speed Grade) 20 ns —
Supply Voltage (VCC) 5.0 V —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) —
Programming Technology EEPROM (non-volatile) —
封装 280-pin PGA (PIN/PEG, square) 280-pin CPGA (Ceramic Pin Grid Array)
Terminal Form PIN/PEG (through-hole PGA) —
Package Code PGA —
Temperature Grade Industrial —
I/O Pin DC Input Range -0.5 V to VCC + 0.5 V —
Dedicated-Input Pin DC Input Range -0.3 V to VCC + 0.3 V —
I/O Transient Envelope (no-load, <20 ns) -2.0 V undershoot to 7.0 V overshoot —
VCC Ramp Requirement Monotonic rise —
Development Tool Altera MAX+PLUS II —
Supported HDLs VHDL, Verilog HDL, AHDL —
RoHS 状态 [DATA_NEEDED: RoHS status for GI PGA package] [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant]
Family — MAX 9000
Device Type — CPLD (Complex Programmable Logic Device)
Maximum User I/O — 212
Pin-to-Pin Delay — 20 ns (speed grade -20)
Counter Frequency (max) — 100 MHz
Supply Voltage (VCCINT) — 4.75 V to 5.25 V (5.0 V nominal)
I/O Voltage — 3.3 V or 5.0 V configurable
Process Technology — CMOS EEPROM
工作温度 — [DATA_NEEDED: commercial/industrial/military grade]
In-System Programming — Yes, via IEEE 1149.1 JTAG
安装类型 — Through-Hole (CPGA socket)

数据手册与资源

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