EPM9560RC208-15C vs EPM9560RC208-10 对比
详细并排对比 EPM9560RC208-15C 出自 Altera 和 EPM9560RC208-10 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9560RC208-15C | EPM9560RC208-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $15.40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD (EPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| User I/O Pins | 149 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Counter Frequency | 117.6 MHz | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Nominal Supply Voltage | 5.0 V | — |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (in-system programmable via JTAG) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| 封装 | 208-pin RQFP | 208-pin RQFP (Plastic Quad Flat Pack) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度范围 | 0C to +70C (commercial) | — |
| Speed Grade | -15 (15 ns) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in retrieved distributor listings] |
| Logic Architecture | Multiple Array MatriX (MAX) third generation | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 (208-pin package variant) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: internal toggle frequency in MHz] |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Standards Supported | — | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| 工作温度 | — | 0C to +70C (commercial) |
| Lead-Free | — | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] |
| Programmability | — | JTAG (IEEE 1149.1) in-system programming |