EPM9560RC208-17 vs EPM9560RC208-15 对比
详细并排对比 EPM9560RC208-17 出自 Altera 和 EPM9560RC208-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM9560RC208-17 | EPM9560RC208-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $54.75 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (EPLD, in-system programmable) | — |
| Usable Gates | 12,000 | 12,000 gates |
| Macro Cells | 560 | 560 macro cells |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 17 ns | — |
| Maximum Counter Frequency | 117.6 MHz | — |
| User I/O Pins | 212 | — |
| Supply Voltage (VCC) | 5 V | — |
| 封装 | 208-pin RQFP (RC208) | 208-pin RQFP (Power Quad Flat Pack) |
| Programming Technology | EEPROM (in-system programmable) | — |
| Program/Erase Cycles | 100 minimum | — |
| JTAG (IEEE 1149.1) Support | Yes | — |
| Architecture | Third-generation MAX (AND-OR PLA) | Third-generation Multiple Array MatriX (MAX) |
| 安装类型 | Surface Mount | Surface Mount |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| 电源电压 | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| 工作温度 | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |