EPM9560RC240-10N vs EPM9560RC240-12 对比
详细并排对比 EPM9560RC240-10N 出自 Intel 和 EPM9560RC240-12 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Intel
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N ⚠ 最后一次采购
规格对比
| 参数 | EPM9560RC240-10N | EPM9560RC240-12 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $168.00 | $9.95 |
| Family | MAX 9000 | MAX 9000 (EPM9560) |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | — |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 20 |
| User I/Os | 212 | — |
| Internal Operating Frequency | 144.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| 电源电压 | 5.0 V | — |
| Process Technology | 0.65 µm CMOS EEPROM | CMOS |
| 封装 | 240-pin RQFP (Plastic Quad Flat Pack) | PQFP-240 (RC240) 0.500 mm pitch, gull-wing |
| Programming Interface | JTAG (IEEE 1149.1) - in-system programmable | IEEE 1149.1 JTAG |
| I/O Standards Supported | 5.0 V TTL/CMOS, 3.3 V PCI-compatible | — |
| Operating Temperature (Commercial) | 0 °C to +70 °C | — |
| Lead-Free Finish (N suffix) | Yes (Pb-free) | — |
| RoHS 状态 | ROHS3 Compliant (per fpgalink.com listing) | [DATA_NEEDED: RoHS compliance] |
| 湿敏等级（MSL） | 3 (168 hours) | — |
| Device Type | — | EE PLD / CPLD |
| Flip-Flops | — | 772 |
| User I/O Pins | — | 191 |
| Maximum Propagation Delay (tPD) | — | 13.4 ns |
| Speed Grade | — | -12 (13.4 ns tPD) |
| Maximum Operating Frequency (estimated) | — | ~76 MHz registered |
| Core Supply Voltage (VCCINT) | — | 5 V |
| I/O Logic Levels | — | 3.3 V or 5 V (configurable) |
| 安装类型 | — | Surface Mount |
| Configuration Memory | — | EEPROM (non-volatile) |
| 工作温度 | — | [DATA_NEEDED: operating temperature grade] |