EPM9560RC240-15YY vs EPM9560RC240-12 对比

详细并排对比 EPM9560RC240-15YY 出自 Intel 和 EPM9560RC240-12 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-15YY EPM9560RC240-12
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $64.50 $9.95
Family MAX 9000A MAX 9000 (EPM9560)
Logic Type CMOS EEPROM-based CPLD —
Number of Macrocells 560 —
Usable Gates 12,000 —
Number of User I/O 191 —
Maximum Operating Frequency 117.6 MHz —
Propagation Delay (tpd) 15 ns —
Supply Voltage (VCC) 5.0 V —
Programmability In-system via IEEE 1149.1 (JTAG) —
Package Type RQFP-240 (Plastic Quad Flat Pack) —
安装类型 Surface Mount Surface Mount
工作温度 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature grade]
Speed Grade -15 -12 (13.4 ns tPD)
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count for EPM9560] 20
RoHS 状态 Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) [DATA_NEEDED: RoHS compliance]
Device Type — EE PLD / CPLD
Macrocells — 560
Flip-Flops — 772
User I/O Pins — 191
Maximum Propagation Delay (tPD) — 13.4 ns
Maximum Operating Frequency (estimated) — ~76 MHz registered
Core Supply Voltage (VCCINT) — 5 V
I/O Logic Levels — 3.3 V or 5 V (configurable)
封装 — PQFP-240 (RC240) 0.500 mm pitch, gull-wing
Configuration Memory — EEPROM (non-volatile)
Programming Interface — IEEE 1149.1 JTAG
Process Technology — CMOS

数据手册与资源

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