EPM9560RC240-15YY vs EPM9560RC240-15N 对比

详细并排对比 EPM9560RC240-15YY 出自 Intel 和 EPM9560RC240-15N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-15YY EPM9560RC240-15N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 不推荐新设计
库存状态 有库存 有库存
单价(USD) $64.50 $27.85
Family MAX 9000A MAX 9000 (third-generation Multiple Array MatriX)
Logic Type CMOS EEPROM-based CPLD —
Number of Macrocells 560 —
Usable Gates 12,000 12,000
Number of User I/O 191 —
Maximum Operating Frequency 117.6 MHz —
Propagation Delay (tpd) 15 ns —
Supply Voltage (VCC) 5.0 V —
Programmability In-system via IEEE 1149.1 (JTAG) In-system programmable (IEEE 1532/JTAG)
Package Type RQFP-240 (Plastic Quad Flat Pack) —
安装类型 Surface Mount Surface Mount
工作温度 0 C to +70 C (commercial) 0C to +70C (Commercial)
Speed Grade -15 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count for EPM9560] 35
RoHS 状态 Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Series — MAX 9000
Macrocells — 560
Maximum User I/O Pins — 216
Pin-to-Pin Propagation Delay (tPD) — 15 ns
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
电源电压 — 5.0 V
Logic Family — CMOS (EEPROM-based)
Boundary-Scan Test — JTAG (IEEE 1149.1)
封装 — RQFP-240 (240-pin Plastic Quad Flat Pack)

数据手册与资源

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