EPM9560RC240-1O vs EPM9560ARI240-10 对比

详细并排对比 EPM9560RC240-1O 出自 Intel 和 EPM9560ARI240-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-1O EPM9560ARI240-10
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $51.07 $0.00
Family MAX 9000 MAX 9000
Usable Gates 12,000 12,000
Macrocells 560 —
Logic Array Blocks (LABs) 35 —
Maximum User I/O Pins 216 —
Propagation Delay (tPD) 12 ns (typ, -1 speed grade) —
Global Setup Time (tFSU) 3.0 ns —
Clock-to-Output (tFCO) 4.8 ns —
Maximum Internal Frequency (fCNT) 145 MHz —
Supply Voltage (VCC) 5.0 V —
Operating Temperature (Grade) -40C to +85C (industrial, "-1O" suffix) —
Process Technology CMOS EEPROM, 0.65 um —
Programming In-system programmable via IEEE 1149.1 JTAG —
Architecture Multiple Array MatriX (MAX), third generation —
封装 RQFP-240 (240-pin Reduced-height QFP) 240-pin RQFP (PowerQuad Flat Pack)
安装类型 Surface Mount Surface Mount
RoHS 状态 Compliant (per Altera/Intel product page) [DATA_NEEDED: RoHS status]
Lead-Free Yes —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 560
User I/O Pins — 191
Pin-to-Pin Propagation Delay — 10 ns
Internal Frequency — 144.9 MHz
电源电压 — 5.0 V
Technology — CMOS, EEPROM-based configuration
工作温度范围 — -40 C to +85 C (industrial)
Configuration Memory — EEPROM (non-volatile, instant-on)
Logic Architecture — Multiple Array MatriX (MAX) with global interconnect array
Moisture Sensitivity Level — [DATA_NEEDED: MSL level]
Number of Terminals — 240
Terminal Form — Gull Wing

数据手册与资源

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