EPM9560RC240-20N vs EPM9560RC240-20 对比

详细并排对比 EPM9560RC240-20N 出自 Altera 和 EPM9560RC240-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560RC240-20N EPM9560RC240-20
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $0.00 $122.00
Device Family MAX 9000 (EPM9560) —
Logic Type Complex Programmable Logic Device (CPLD) —
Macrocells 560 —
Usable Gates 12,000 —
Logic Array Blocks (LABs) 35 —
Maximum User I/O Pins 216 —
Pin-to-Pin Propagation Delay (tPD1) 20 ns —
Internal Counter Frequency (fCNT) 144 MHz —
Flip-Flop Setup Time (tSU) 3.0 ns —
电源电压 5.0 V —
Configuration Technology EEPROM (in-system programmable) —
封装 240-pin RQFP (PowerQuad Flat Pack) —
工作温度 0 C to +70 C (commercial) 0C to 70C (Commercial)
安装类型 Surface Mount Surface Mount
Speed Grade -20 (20 ns) —
RoHS 状态 [DATA_NEEDED: RoHS status] —
Lead-Free Status [DATA_NEEDED: lead-free status] —
Family — MAX 9000
Series — MAX 9000 PLD Family
Programmable Type — In System Programmable
Number of Macrocells — 560
Number of Gates — 12,000
Number of Logic Elements/Blocks — 35 LABs
Number of User I/Os — 191
Propagation Delay (tPD max) — 20 ns
Maximum Internal Frequency — 100 MHz
Supply Voltage (VCCINT) — 4.75 V to 5.25 V
Technology — CMOS, EEPROM-based
封装 / 外壳 — 240-BFQFP Exposed Pad (RQFP-240)
Supplier Device Package — 240-RQFP
Programming Interface — JTAG (IEEE 1149.1), Altera proprietary
Product Status — Obsolete
Lead-Free / RoHS — [DATA_NEEDED: RoHS status for this lot]

数据手册与资源

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