EPM9560RC240-20N vs EPM9560RI240-20N 对比

详细并排对比 EPM9560RC240-20N 出自 Altera 和 EPM9560RI240-20N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM9560RI240-20N EPM9560RI240-20N - MAX 9000 CPLD, 560 Macro, 191 I/O | Intel

EPM9560RI240-20N - MAX 9000 CPLD, 560 Macro, 191 I/O | Intel

EPM9560RI240-20N ⚠ 最后一次采购

规格对比

参数 EPM9560RC240-20N EPM9560RI240-20N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $0.00 $195.00
Device Family MAX 9000 (EPM9560) —
Logic Type Complex Programmable Logic Device (CPLD) —
Macrocells 560 560
Usable Gates 12,000 —
Logic Array Blocks (LABs) 35 12
Maximum User I/O Pins 216 —
Pin-to-Pin Propagation Delay (tPD1) 20 ns —
Internal Counter Frequency (fCNT) 144 MHz —
Flip-Flop Setup Time (tSU) 3.0 ns —
电源电压 5.0 V —
Configuration Technology EEPROM (in-system programmable) —
封装 240-pin RQFP (PowerQuad Flat Pack) 240-pin Power-enhanced BGA (RI240)
工作温度 0 C to +70 C (commercial) 0C to +70C (commercial)
安装类型 Surface Mount —
Speed Grade -20 (20 ns) —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Lead-Free Status [DATA_NEEDED: lead-free status] —
Family — MAX 9000
Architecture — Multiple Array MatriX (MAX) - third generation
User I/Os — 191
Maximum Internal Frequency — 145 MHz
Pin-to-Pin Propagation Delay (tPD) — 11.4 ns
Logic Family — CMOS
Process Technology — CMOS EEPROM
Programmability — In-system programmable (ISP) via JTAG (IEEE 1149.1)
Core Supply Voltage — 5.0 V
MultiVolt I/O — 5.0 V / 3.3 V compatible
Programming Language Support — AHDL, VHDL, Verilog HDL
Development Tools — MAX+PLUS II, Quartus II

数据手册与资源

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