EPM9560SRC240-15 vs EPM9560RI240-15 对比

详细并排对比 EPM9560SRC240-15 出自 Altera 和 EPM9560RI240-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560SRC240-15 EPM9560RI240-15
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $22.50 $23.10
Family MAX 9000 MAX 9000
Device Type EPLD / CPLD (Complex Programmable Logic Device) —
Usable Gates 560 —
Logic Array Blocks (LABs) 16 —
Macrocells 212 560
Maximum User I/O Pins [DATA_NEEDED: exact I/O count for SRC240 package] —
Speed Grade -15 (15 ns tPD) —
Pin-to-Pin Logic Delay (tPD) 15 ns (max) —
Supply Voltage (VCC) 5 V (nominal) —
Programmability In-system programmable via IEEE 1149.1 JTAG —
Non-volatile Yes (EPROM/EEPROM cells) —
封装 RQFP-240 (Surface Mount) RQFP-240 (Power Quad Flat Pack, gull-wing, 0.500 mm pitch)
工作温度 [DATA_NEEDED: commercial 0-70C or industrial -40-85C] -40 C to +85 C (industrial)
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS compliance not stated in provided data] —
Process Technology CMOS EPROM —
Product Type — EE PLD (Electrically Erasable Programmable Logic Device)
Flip-Flops — 772
User I/Os (industrial grade) — 191
Dedicated Inputs — 4
Propagation Delay (tPD) — 15 ns (speed grade -15)
Internal Frequency (max) — 145 MHz
Logic Family / Process — CMOS, EEPROM-based
Core Voltage — 5.0 V
I/O Voltage — 3.3 V or 5.0 V (configurable)
Architecture — Multiple Array MatriX (MAX), 3rd generation
In-System Programmability — Yes, JTAG (IEEE Std 1149.1)
Power-Up Configuration — Instant-on (no external boot PROM)
I/O Undershoot Tolerance — -2.0 V for <20 ns (no-load)
I/O Overshoot Tolerance — 7.0 V for <20 ns (no-load)

数据手册与资源

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