LCMXO2-1200HC-4TG100C vs LCMXO2-640HC-4TG100C 对比
详细并排对比 LCMXO2-1200HC-4TG100C 出自 Lattice Semiconductor 和 LCMXO2-640HC-4TG100C 出自 Lattice Semiconductor。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Lattice Semiconductor
LCMXO2-1200HC-4TG100C - 1280-LUT 3.3V FPGA | Lattice
LCMXO2-1200HC-4TG100C ✓ 量产中Lattice Semiconductor
LCMXO2-640HC-4TG100C - 640 LUT MachXO2 FPGA, 100-LQFP | Lattice
LCMXO2-640HC-4TG100C ✓ 量产中规格对比
| 参数 | LCMXO2-1200HC-4TG100C | LCMXO2-640HC-4TG100C |
|---|---|---|
| 品牌 | Lattice Semiconductor | Lattice Semiconductor |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $13.45 | $5.10 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | MachXO2 | — |
| Logic Cells | 1,280 cells | — |
| LUT Count | 1,280 LUTs | — |
| Available I/O | 79 I/O | — |
| User Memory | 256 kbits | — |
| Distributed RAM | Up to 54 kbits | Up to 18.4 kbits (640 LUTs x 32 bits) |
| Dedicated FIFO Control Logic | Supported | — |
| 电源电压 | 3.3 V | — |
| Speed Grade | -4 | — |
| Technology | Advanced 65 nm low-power process | — |
| Standby Power | As low as 22 uW | As low as 22 µW |
| I/O Feature | Programmable low-swing differential I/O | — |
| Power-Saving Modes | Standby mode and other power-saving options | — |
| 工作温度 | 0 C to 85 C junction | 0C to +85C (Commercial, C suffix) |
| 封装 | TG100, 100-pin TQFP, 14 x 14 mm | 100-pin TQFP (TG100), 14 x 14 mm |
| 安装类型 | Surface Mount | — |
| Voltage Variant | 2.5 V or 3.3 V external VCC supply for HC family | — |
| RoHS | RoHS listed by the Micros product excerpt | — |
| Family | — | MachXO2 |
| Logic Elements / LUTs | — | 640 LUTs (4-input) |
| Number of PLDs (Logic Blocks) | — | 80 |
| Embedded Block RAM (EBR) | — | 18,432 bits (2 x 9 kbit blocks) |
| Number of User I/Os | — | 78 |
| Number of Macrocells | — | 320 |
| Maximum Operating Frequency | — | 136.6 MHz |
| Programmable Type | — | In System Programmable (Flash + SRAM) |
| Core Voltage (Vcc) | — | 3.3 V (typical HC grade) |
| I/O Voltage (Vccio) | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | LVCMOS 1.2-3.3 V, LVDS, LVPECL, programmable differential |
| Process Technology | — | 65 nm low-power CMOS |
| Configuration Memory | — | On-chip Flash (non-volatile) + SRAM |
| Lead-Free / RoHS | — | Lead Free, RoHS Compliant |
| 无卤 | — | Yes (per Lattice MachXO2 family datasheet) |