LS1021AXE7HNB vs LS1021AXE7HNB557 对比
详细并排对比 LS1021AXE7HNB 出自 NXP Semiconductors 和 LS1021AXE7HNB557 出自 NXP Semiconductors。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
NXP Semiconductors
LS1021AXE7HNB557 - QorIQ LS1021A 800MHz Dual Cortex-A7 MPU | NXP
LS1021AXE7HNB557 ✓ 量产中规格对比
| 参数 | LS1021AXE7HNB | LS1021AXE7HNB557 |
|---|---|---|
| 品牌 | NXP Semiconductors | NXP Semiconductors |
| 分类 | Microcontrollers | Microcontrollers |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $40.05 | $21.20 |
| Core Architecture | ARM Cortex-A7 (dual-core) | ARM Cortex-A7 (dual-core), 32-bit |
| Maximum CPU Frequency | 800 MHz | — |
| 工作温度范围 | -40 C to +105 C (industrial) | — |
| 封装 | 525-FCPBGA (19x19 mm) | 525-FCPBGA, 19x19 mm, 0.8 mm pitch |
| Memory Interface | DDR3L / DDR4 with ECC, up to 1600 MT/s | — |
| Cache (per core) | 32 KB I-cache + 32 KB D-cache | — |
| Ethernet | 2x 10/100/1000 MAC (vTSEC, TSN-ready) | 3x vTSEC Gigabit Ethernet MACs |
| PCIe | 3x PCIe 2.0 controllers | PCIe Gen 2.0 root complex + endpoint |
| USB | 1x USB 3.0 + 1x USB 2.0 (with PHY) | USB 3.0 + USB 2.0 with PHY |
| SATA | 2x SATA 3.0 (6 Gbps) | SATA 3.0 (1x port) |
| LCDC | Integrated, up to 1920x1080 | — |
| Cryptographic Offload | SEC 5.x (IPSec/SSL/TLS/DTLS acceleration) | — |
| Other Interfaces | CAN, uQE, I2C, SPI, UART, QSPI, SD/MMC | — |
| Silicon Revision | Rev 2.0 | — |
| 安装类型 | Surface Mount (FCPBGA) | — |
| MSL 等级 | 3 (per JEDEC J-STD-020) | — |
| RoHS 状态 | Compliant | Compliant |
| Maximum Core Frequency | — | 800 MHz |
| L1 Cache (per core) | — | [DATA_NEEDED: 32 KB I-cache + 32 KB D-cache per datasheet family] |
| L2 Cache (shared) | — | [DATA_NEEDED: 512 KB shared L2 per LS1 family docs] |
| Memory Controller | — | DDR3L / DDR4 with ECC, up to 16-bit |
| Display Controller | — | LCDC + 2D-ACE graphics accelerator |
| CAN | — | 2x CAN-FD controllers |
| Security Engine | — | SEC (AES, 3DES, SHA, RSA, ECC) |
| 工作温度 | — | -40C to +105C (industrial) |
| Series | — | QorIQ Layerscape LS1 |