RTAX2000SL-1CGS624B vs RTAX2000S-1CGS624EV 对比
详细并排对比 RTAX2000SL-1CGS624B 出自 Microchip Technology 和 RTAX2000S-1CGS624EV 出自 Microchip Technology。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Microchip Technology
RTAX2000SL-1CGS624B - Rad-Tolerant FPGA 2M Gates CCGA624 | Microchip
RTAX2000SL-1CGS624B ✓ 量产中Microchip Technology
RTAX2000S-1CGS624EV - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000S-1CGS624EV ✓ 量产中规格对比
| 参数 | RTAX2000SL-1CGS624B | RTAX2000S-1CGS624EV |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $0.00 | $3,600.00 |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| Logic Blocks (CLBs) | 21504 | — |
| Equivalent System Gates | 2000000 | — |
| ASIC Gates | 250000 | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V nominal (1.425 V to 1.575 V) |
| Speed Grade | -1 | — |
| 最大时钟频率 | 649 MHz (family max, Jotrin listing) | — |
| Programmability | One-Time Programmable (antifuse) | — |
| Configuration | Live at power-up, single-chip | One-time programmable anti-fuse, live at power-up, single chip |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Radiation Tolerance | Radiation-tolerant (space-flight qualified family) | — |
| 封装 | 624-pin Ceramic Column Grid Array (CCGA / CGA-624, ceramic) | 624-pin Ceramic Column Grid Array (CGA-624 / CCGA624) |
| 安装类型 | Surface Mount | Surface Mount |
| 工作温度 | [DATA_NEEDED: operating temperature range] | -55C to +125C |
| I/O Count | [DATA_NEEDED: user I/O count] | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| System Gates | — | 2,000,000 |
| Logic Cells (CLBs) | — | 21504 |
| Total Cells | — | 32256 |
| Additional ASIC Equivalent Gates | — | 250000 |
| Maximum Frequency | — | 649 MHz |
| Logic Family | — | CMOS |
| SEU Immunity | — | SEU-hardened registers, immune to single-event upsets to specified LET threshold |
| SEU Rate | — | < 10-10 errors/bit-day |
| Product Family | — | RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs |
| Thermal Resistance Basis | — | JEDEC JESD51 simulation conditions (per datasheet) |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |
| Maximum User I/O | — | [DATA_NEEDED: user I/O count] |