XC6SLX45-2FG484I vs XC6SLX45-2FGG484I 对比

详细并排对比 XC6SLX45-2FG484I 出自 Xilinx 和 XC6SLX45-2FGG484I 出自 AMD。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 XC6SLX45-2FG484I XC6SLX45-2FGG484I
品牌 Xilinx AMD
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Unknown 有效
Device Type Spartan-6 LX Field Programmable Gate Array (FPGA) —
Logic Cells 43,661 cells 43,661
Number of I/O 316 I/O —
Listed Internal Frequency 500 MHz —
Process Technology 45 nm CMOS 45 nm low-power CMOS
Core Operating Voltage 1.2 V —
Device Family Spartan-6 LX —
Speed Grade -2 -2
Temperature Grade Industrial —
工作温度范围 -40°C to +100°C (junction temperature) —
封装 484-BBGA 484-ball BGA (FBGA-484)
安装类型 Surface mount —
Package Pitch 0.80 mm —
Package Lead-Free Status Lead free —
Number of Logic Cells in Alternative Comparison 43,661 cells —
Adaptive Logic Modules [DATA_NEEDED: Adaptive Logic Module count] —
Embedded Memory [DATA_NEEDED: Embedded block RAM capacity] —
DSP Resources [DATA_NEEDED: DSP slice count] —
Configuration Memory [DATA_NEEDED: Configuration memory type and capacity] AES-256 bitstream encryption
RoHS 状态 [DATA_NEEDED: RoHS compliance status] —
REACH Status [DATA_NEEDED: REACH compliance status] —
AEC-Q100 Status [DATA_NEEDED: AEC-Q100 qualification status] —
Family — Spartan-6 LX
Logic Slices — 6,822
Flip-Flops — 54,576
Block RAM — 2,138,112 bits (2,088 Kb/s)
DSP Slices (DSP48A1) — 58
Maximum User I/O — 316
Package Dimensions — 23 x 23 mm, 1.0 mm ball pitch
Operating Temperature (I grade) — -40C to +100C (industrial)
Supply Voltage Core — 1.2 V typical
Clock Management Tiles — 6 CMT (4 DCM + 2 PLL)
Maximum I/O Speed — 800 Mbps LVDS
Memory Interface Support — DDR, DDR2, DDR3, LPDDR
RoHS Compliance — Lead-free / RoHS compliant

数据手册与资源

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