XC6SLX9-2TQG144I vs XC6SLX4-2TQG144I 对比
详细并排对比 XC6SLX9-2TQG144I 出自 AMD 和 XC6SLX4-2TQG144I 出自 AMD。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | XC6SLX9-2TQG144I | XC6SLX4-2TQG144I |
|---|---|---|
| 品牌 | AMD | AMD |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | Unknown |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $16.20 | $6.19 |
| Family | Spartan-6 LX | — |
| Logic Cells | 9,152 | 3,840 cells |
| Slices / ALMs | 1,430 ALMs (715 CLBs) | — |
| Block RAM | 576 Kbits (72 x 18 Kb) | 221,184 bits |
| DSP Slices | 16 (DSP48A1) | — |
| Maximum User I/O | 102 | — |
| 封装 | 144-pin TQFP (TQG144), 20 x 20 mm, 0.5 mm pitch | 144-pin TQFP |
| Speed Grade | -2 (mid-range) | -2 |
| 工作温度 | -40C to +100C (Industrial) | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Bank Voltage (VCCO) | 1.2 V to 3.3 V | — |
| Process Technology | 45 nm low-power CMOS (9-metal copper) | 45 nm |
| Memory Interfaces | DDR, DDR2, DDR3, LPDDR (via Memory Controller Block) | — |
| Clock Management | DCM + PLL per tile | — |
| 安装类型 | Surface Mount | — |
| MSL 等级 | 3 (per JEDEC J-STD-020) | — |
| RoHS 状态 | RoHS Compliant (Lead Free) | — |
| Device Type | — | Spartan-6 LX field-programmable gate array (FPGA) |
| Available I/O | — | 102 pins |
| 最大时钟频率 | — | 375 MHz |
| 电源电压 | — | 1.14 V to 1.26 V |
| Package Body Size | — | 20 mm x 20 mm |
| Package Pitch | — | 0.5 mm |
| Clocking Resources | — | DCM and PLL resources |
| Configuration Memory | — | SRAM-type internal latches |
| Memory Controller | — | No memory controller in XC6SLX4 |
| Temperature Grade | — | Industrial |
| Lead-Free Status | — | Lead-free |
| Technology | — | CMOS |
| Configuration Interface | — | FPGA configuration resources; detailed interface data not provided |
| I/O Standard | — | [DATA_NEEDED: supported I/O standards] |
| 工作温度范围 | — | [DATA_NEEDED: operating temperature range] |