74VHC373MTCX - Octal D-Type Latch, 3-STATE, TSSOP-20 | onsemi
料号： 74VHC373MTCX ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0.61 | $0.61 |
| 10 | $0.55 | $5.50 |
| 100 | $0.43 | $43.00 |
| 500 | $0.36 | $180.00 |
| 1,000 | $0.32 | $320.00 |
| 2,500 | $0.29 | $725.00 |
74VHC373MTCX 概述
A D-type transparent latch is a sequential logic element that captures data on its D inputs when the latch-enable signal is asserted, and holds that data on the Q outputs when LE is de-asserted. The 3-STATE outputs allow multiple devices to share a common bus, controlled by the OE pin. In the broader system hierarchy, the 74VHC373 belongs to the 74VHC logic family of high-speed CMOS logic, itself part of the larger CMOS logic IC family used for glue logic, bus buffering, and address/data demultiplexing in digital systems.
Key specifications include a wide 2.0 V to 5.5 V VCC operating range, typical propagation delay of approximately 5 ns at 5 V, low quiescent current, and high output drive capability. The output structure is non-inverting, making it well suited to bus-driving applications where input and output polarities must match. An internal static-guard design provides ESD protection on every input and output pin.
Typical applications include address/data bus demultiplexing in microcontroller and microprocessor systems, bus arbitration and bidirectional buffering, register file building blocks, I/O port expansion, and general-purpose storage elements in digital logic designs. The TSSOP-20 footprint makes it attractive for compact, surface-mount assemblies where board space is constrained.
When designing with this part, ensure that the OE pin is correctly driven to avoid bus contention when multiple 74VHC373 devices share a common output bus. Decoupling the VCC pin with a 0.1 µF ceramic capacitor placed within a few millimeters of the package is recommended for reliable high-speed operation.
This page synthesizes distributor pricing, verified cross-reference drop-in alternatives, and practical design notes beyond what is presented in the manufacturer datasheet.
直接替换替代料： 74VHC373MTCX ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： 74VHC373MTCX （相同外形与封装尺寸） ——差异在于 Input Type, Logic Family, Number of Channels, Operating Temperature, Output Type.
快速对比工具——选择替代料号进行并排对比：
74VHC373MTC
✅ 直接替换📋 参考替代料（不在目录中）
MC74VHC373DTR2G
✅ 直接替换📋 参考替代料（不在目录中）
SN74AHC373PWG4
✅ 直接替换📋 参考替代料（不在目录中）
74VHC373MTCX 最大额定值与电气特性
| Logic Type | D-Type Transparent Latch |
| Number of Channels | 1 |
| Number of Bits per Channel | 8 |
| 输出配置 | 3-State (Tri-State) |
| 输出类型 | Non-Inverting |
| Latch Type | Transparent D-Type |
| VCC Supply Range | 2.0 V to 5.5 V |
| Logic Family | 74VHC (High-Speed CMOS) |
| Input Type | CMOS |
| 工作温度 | -40 °C to +85 °C |
| 安装类型 | Surface Mount |
| 封装 | 20-TSSOP (MTC), 4.40 mm body width |
| RoHS 状态 | Compliant |
| Lead-Free | Yes |
74VHC373MTCX 引脚配置
| 引脚 1 | OE — Output Enable (active LOW for 3-STATE outputs; HIGH = outputs high-impedance) |
| 引脚 2 | D0 — Data input bit 0 |
| 引脚 3 | D1 — Data input bit 1 |
| 引脚 4 | D2 — Data input bit 2 |
| 引脚 5 | D3 — Data input bit 3 |
| 引脚 6 | D4 — Data input bit 4 |
| 引脚 7 | D5 — Data input bit 5 |
| 引脚 8 | D6 — Data input bit 6 |
| 引脚 9 | D7 — Data input bit 7 |
| 引脚 10 | GND — Ground reference |
| 引脚 11 | LE — Latch Enable (active HIGH; data flows D to Q while HIGH, held when LOW) |
| 引脚 12 | Q0 — Latch output bit 0 (3-STATE) |
| 引脚 13 | Q1 — Latch output bit 1 (3-STATE) |
| 引脚 14 | Q2 — Latch output bit 2 (3-STATE) |
| 引脚 15 | Q3 — Latch output bit 3 (3-STATE) |
| 引脚 16 | Q4 — Latch output bit 4 (3-STATE) |
| 引脚 17 | Q5 — Latch output bit 5 (3-STATE) |
| 引脚 18 | Q6 — Latch output bit 6 (3-STATE) |
| 引脚 19 | Q7 — Latch output bit 7 (3-STATE) |
| 引脚 20 | VCC — Power supply (2.0 V to 5.5 V) |
典型应用
74VHC373MTCX 适用于 6 应用s: Microprocessor Address/Data Bus Demultiplexing, Bus Arbitration and Bidirectional Buffering, I/O Port Expansion, Register File Building Block, Industrial Control Logic, Test and Measurement Equipment.
Microprocessor Address/Data Bus Demultiplexing
The 74VHC373MTCX is a classic building block for demultiplexing the multiplexed address/data bus of 80C31/8051 microcontrollers and similar processors. The 8-bit transparent latch captures the low-byte address on D0-D7 when LE is asserted during the ALE cycle, then holds that address on the Q0-Q7 outputs for the remainder of the bus cycle so the processor can use the bus for data transfer. The 3-STATE OE control allows the latch outputs to be released when an external memory device takes over the bus, preventing contention. Operating from 2.0 V to 5.5 V, the device works seamlessly with both 5 V 8051 systems and 3.3 V modern microcontrollers. The CMOS low-power dissipation reduces overall system current draw compared to legacy bipolar 74LS373 designs, while matching TTL-compatible switching speeds.
推荐
Bus Arbitration and Bidirectional Buffering
The 74VHC373MTCX serves as a unidirectional 8-bit latch in bidirectional bus architectures where multiple masters must arbitrate for shared resources. By connecting the OE pins of multiple 74VHC373 devices to arbitration logic, only one source drives the shared bus at any time. The transparent latch function isolates the held value from upstream bus transients during read cycles, improving signal integrity on heavily loaded buses. The wide VCC range (2.0-5.5 V) supports mixed-voltage systems where legacy 5 V peripherals share a 3.3 V processor bus. The TSSOP-20 package provides compact routing in dense backplane designs where multiple parallel latches must fit adjacent to connector pins.
推荐
I/O Port Expansion
For microcontroller designs needing additional output ports without integrated peripherals, the 74VHC373MTCX provides 8 bits of latched output expansion through just three control pins (LE, OE, D-input). The micro writes data to the latch via a GPIO port, strobes LE briefly to capture, and the 74VHC373MTCX holds the output state indefinitely. This pattern is widely used in LED driving, relay control, and parallel LCD interface circuits. The 3-STATE OE control lets the expansion port be electrically disconnected when not in use, eliminating bus contention during shared peripheral access. Compared to shift-register expansion (e.g., 74HC595), the parallel latch interface is faster for simultaneous 8-bit updates, at the cost of using more GPIO pins.
推荐
Register File Building Block
The 74VHC373MTCX functions as one byte of a register file when multiple devices are cascaded or arranged with external decoding. Designers use the device to build small general-purpose register banks for DSP, FPGA glue logic, or custom state machines. The transparent latch captures data on the rising edge of LE, then holds it on Q outputs; this acts as an edge-triggered register when LE is driven by a clock edge. Combined with an external decoder (such as 74HCT154BQ), multiple 74VHC373 latches can be selected individually for read/write operations, creating indexed register files of arbitrary depth.
推荐
Industrial Control Logic
In industrial automation systems, the 74VHC373MTCX interfaces control logic signals to actuator drivers and indicator panels. The wide operating temperature range of -40 °C to +85 °C supports factory floor environments, while the 5.5 V tolerant inputs accept long cable-driven signals without damage. The CMOS low quiescent current reduces power consumption in always-on industrial controllers. A typical configuration latches 8 bits of control state from a PLC CPU and drives opto-isolated actuator inputs downstream. The TSSOP-20 package saves PCB area in densely populated control boards where dozens of signal lines must be routed to terminal blocks.
推荐
Test and Measurement Equipment
The 74VHC373MTCX captures and holds digital test patterns in automated test equipment (ATE), logic analyzers, and laboratory instrumentation. The transparent latch function, combined with the 3-STATE output, allows a stimulus vector to be applied to a device under test and then isolated after capture. Designers use multiple cascaded 74VHC373 devices to build long shift-register patterns for serial-to-parallel conversion in high-channel-count test systems. The low propagation delay through the latch preserves timing fidelity in sub-microsecond test sequences. The TSSOP-20 footprint suits compact probe cards and modular instrumentation where space is at a premium.
推荐
推荐产品汇总
工程参考数据： 74VHC373MTCX ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | 74VHC373MTC | MC74VHC373DTR2G | SN74AHC373PWG4 |
|---|---|---|---|---|
| Package | 20-TSSOP (MTC) | 20-TSSOP (MTC) - same | 20-TSSOP (DT) - same footprint | 20-TSSOP (PW) - same footprint |
| Brand | onsemi | onsemi - same | onsemi - same | Texas Instruments - cross-brand |
| Logic Function | Octal D-Type Transparent Latch | Octal D-Type Transparent Latch - identical | Octal D-Type Transparent Latch - identical | Octal D-Type Transparent Latch - identical |
| Logic Family | 74VHC (VHC) | 74VHC (VHC) - same | 74VHC (VHC) - same | 74AHC (AHC) - cross-family |
| Output Configuration | 3-State, non-inverting | 3-State, non-inverting - identical | 3-State, non-inverting - identical | 3-State, non-inverting - identical |
| VCC Range | 2.0 V to 5.5 V | 2.0 V to 5.5 V - same | 2.0 V to 5.5 V - same | 2.0 V to 5.5 V - same |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C - same | -40 °C to +85 °C - same | -40 °C to +85 °C - same |
| Packaging Carrier | Tape & Reel (MTCX suffix) | Tube (MTC suffix) | Tape & Reel (DTR2 suffix) | Tape & Reel (G4 suffix) |
| Pin-to-Pin Compatible | Reference | Yes - identical pinout | Yes - same TSSOP-20 footprint | Yes - same TSSOP-20 footprint |
关键差异点
- Tube-packaging drop-in option with identical die （对比 74VHC373MTC)
- Same-brand alternative with verified pin-to-pin compatibility （对比 MC74VHC373DTR2G)
- Cross-brand AHC-family option with same TSSOP-20 footprint （对比 SN74AHC373PWG4)
设计说明
Decouple the VCC pin (pin 20) with a 0.1 µF X7R ceramic capacitor placed within 5 mm of the package, plus a bulk 1-10 µF tantalum or electrolytic capacitor on the same VCC net. For multi-latch designs with several 74VHC373 devices sharing a VCC rail, add additional bulk capacitance to absorb simultaneous switching transients. The VHC family draws higher dynamic current during transitions than HC; the bulk cap prevents VCC droop when all 8 bits switch simultaneously.
Do not leave the OE pin (pin 1) floating; an undriven OE may sit at an intermediate voltage causing high quiescent current and unpredictable 3-STATE behavior. Tie OE to GND (LOW) for always-enabled outputs, or drive it from a defined logic source. Also note that LE (pin 11) is level-sensitive: while HIGH, the latch is transparent and Q follows D; only on the HIGH-to-LOW transition is the data latched. Designers intending edge-triggered behavior must ensure LE is a clean narrow pulse, not a slow ramp or noisy signal.
The TSSOP-20 package requires careful PCB layout to maintain signal integrity at high switching speeds. Keep data and output traces short and direct, with ground plane reference for impedance control. Avoid running high-frequency switching signals parallel to sensitive analog traces; the VHC family's ~5 ns edge rates can couple significant noise into nearby circuits. For bus-sharing applications, place the 74VHC373 outputs close to the bus connector and keep stub lengths minimal to reduce reflections.
合规信息
RoHS compliant and lead-free per onsemi product page and distributor listings. Not AEC-Q100 qualified - the 74VHC373MTCX is not designed for automotive applications. For automotive latch needs, look for AEC-Q100 qualified equivalents. Halogen-free status not explicitly stated in verified data.
