AD1555BPRL - 24-Bit Sigma-Delta ADC with PGA | Analog Devices
料号： AD1555BPRL ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $22.1 | $2,210.00 |
| 500 | $19.8 | $9,900.00 |
| 1,000 | $17.95 | $17,950.00 |
AD1555BPRL 概述
An ADC (Analog-to-Digital Converter) is a semiconductor device that converts continuous analog signals into discrete digital codes. Sigma-delta (Σ-Δ) ADCs use oversampling and noise-shaping to achieve very high resolution and dynamic range, making them ideal for low-frequency precision measurement. Within the converter hierarchy, the AD1555BPRL belongs to the precision-measurement ADC family, which sits under data converters and the broader category of analog signal chain ICs.
Key features include 80 nV/√Hz input-referred noise at 4 ms conversion time with a gain of 128, −111 dB maximum / −120 dB typical total harmonic distortion, and 122 dB intermodulation distortion. The integrated PGA supports gains up to 128, allowing direct interfacing with low-level bridge, strain-gauge, and thermocouple sensors without external instrumentation amplifiers. The ones-density bitstream output pairs with the AD1556 digital filter to reconstruct 24-bit conversion results.
The fourth-order modulator uses a switched-capacitor architecture with continuous-time calibration for low drift over temperature. The device operates from ±5 V analog supplies and a +3 V to +5 V digital supply, with the PLCC-28 package providing a thermal resistance suitable for industrial environments from −40 °C to +85 °C.
Typical applications include seismic instrumentation, weigh scales, high-precision industrial process control, and low-frequency vibration analysis. The 120 dB dynamic range enables direct digitization of bridge outputs without front-end gain stages.
When designing with this device, pair the AD1555BPRL with the AD1556 companion digital filter ASIC to obtain a complete 24-bit ADC solution. Provide separate analog and digital ground planes, decouple each supply pin with 10 µF tantalum in parallel with 0.1 µF ceramic, and keep the analog input traces away from the digital bitstream output to preserve 120 dB dynamic range.
This page synthesizes distributor pricing, drop-in package alternatives, application circuits, and design notes not consolidated on the manufacturer product page.
直接替换替代料： AD1555BPRL ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
AD1555APRL
✅ 直接替换📋 参考替代料（不在目录中）
AD1555BPZ
✅ 直接替换📋 参考替代料（不在目录中）
AD1555BPRL-1
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AD1556APZ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AD1871YRS
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AD1555BPRL 最大额定值与电气特性
| 分辨率 | 24-bit |
| Converter Type | Sigma-Delta Modulator (fourth-order) |
| Dynamic Range | 116 dB min / 120 dB typical |
| 采样率 | 256 kHz (max) |
| Input-Referred Noise | 80 nV/√Hz (gain = 128, 4 ms conversion) |
| Total Harmonic Distortion | -111 dB max / -120 dB typical |
| Intermodulation Distortion | 122 dB |
| Integrated PGA Gain Range | 1 to 128 |
| Number of ADC Channels | 1 |
| Analog Supply Voltage | ±5 V |
| Digital Supply Voltage | +3 V to +5 V |
| Output Interface | Ones-density bitstream (paired with AD1556 digital filter) |
| 工作温度范围 | -40 °C to +85 °C |
| 封装 | 28-pin PLCC |
| 安装类型 | Surface Mount |
AD1555BPRL 引脚配置
| 引脚 1 | AIN+ — Analog positive input |
| 引脚 2 | AIN- — Analog negative input |
| 引脚 3 | REFIN — Reference input |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | AVDD — +5 V analog supply |
| 引脚 6 | AVSS — -5 V analog supply |
| 引脚 7 | PGAOUT — PGA output (internal test) |
| 引脚 8 | NC — Not connected |
| 引脚 9 | NC — Not connected |
| 引脚 10 | MCLK — Master clock input |
| 引脚 11 | DGND — Digital ground |
| 引脚 12 | DVDD — +3 V to +5 V digital supply |
| 引脚 13 | BSOUT — Bitstream output (to AD1556) |
| 引脚 14 | BSOUT-2 — Differential bitstream output |
| 引脚 15 | NC — Not connected |
| 引脚 16 | SYNC — Synchronization input |
| 引脚 17 | PGA0 — PGA gain select bit 0 |
| 引脚 18 | PGA1 — PGA gain select bit 1 |
| 引脚 19 | PGA2 — PGA gain select bit 2 |
| 引脚 20 | NC — Not connected |
| 引脚 21 | NC — Not connected |
| 引脚 22 | NC — Not connected |
| 引脚 23 | NC — Not connected |
| 引脚 24 | NC — Not connected |
| 引脚 25 | NC — Not connected |
| 引脚 26 | NC — Not connected |
| 引脚 27 | TEST1 — Factory test pin (float) |
| 引脚 28 | TEST2 — Factory test pin (float) |
典型应用
AD1555BPRL 适用于 6 应用s: Seismic Instrumentation, Industrial Weigh Scales, Precision Process Control, Vibration Analysis, Thermocouple Measurement Systems, High-Resolution Data Acquisition Systems.
Seismic Instrumentation
The AD1555BPRL's 120 dB typical dynamic range and 80 nV/√Hz input noise at PGA gain 128 make it ideal for seismic sensor digitizers, where ground-motion signals span microvolts to millivolts. Placed between geophone or accelerometer output and the AD1556 digital filter, it delivers 24-bit resolution at 256 kHz maximum sampling, capturing low-frequency seismic events from 0.1 Hz to several hundred Hz with full dynamic-range fidelity. The fourth-order modulator noise-shaping preserves 120 dB across the seismic measurement passband.
推荐
Industrial Weigh Scales
With 116 dB minimum dynamic range and integrated PGA gain up to 128, the AD1555BPRL directly digitizes load-cell bridge outputs without external instrumentation amplifiers, reducing BOM cost. In a typical 4-wire weigh-scale platform, the device connects across the bridge differential output, with the AD1556 providing the digital filter at user-selectable output rates (typically 10 Hz or 50 Hz). The 80 nV/√Hz noise floor enables 1 mg resolution in 100 kg-class industrial scales.
推荐
Precision Process Control
The AD1555BPRL's -111 dB maximum THD and 122 dB intermodulation make it ideal for high-precision process-control loops, digitizing strain-gauge and load-cell transducer outputs in real-time control systems. Operating from ±5 V analog and +3 V digital supplies, it provides galvanically isolated analog front-end when paired with digital isolation. The 24-bit output at 256 kHz sampling supports closed-loop control bandwidths up to several kHz in industrial PLC modules.
推荐
Vibration Analysis
For low-frequency vibration analysis of rotating machinery, the AD1555BPRL provides 24-bit resolution and 120 dB dynamic range needed to capture micro-g accelerometer outputs across the 1 Hz to 10 kHz mechanical-vibration band. The PGA gain up to 128 lets engineers match the sensor output to the ADC full-scale input without external amplifiers. The ones-density bitstream feeds the AD1556 filter for synchronous decimation at selectable rates for FFT analysis.
推荐
Thermocouple Measurement Systems
With 80 nV/√Hz input noise at maximum PGA gain and 24-bit resolution, the AD1555BPRL provides sufficient sensitivity to digitize microvolt-level thermocouple outputs (Type K, Type J, etc.) for high-accuracy temperature measurement. The integrated PGA replaces dedicated thermocouple amplifiers, simplifying the analog front-end. The device's -40 °C to +85 °C operating range and the AD1556 digital filter's selectable notch frequencies enable simultaneous 50/60 Hz rejection.
推荐
High-Resolution Data Acquisition Systems
The AD1555BPRL plus AD1556 pair delivers a complete 24-bit sigma-delta ADC function for multi-channel precision data-acquisition front-ends, where 120 dB dynamic range enables simultaneous acquisition of high-amplitude and low-amplitude signals. The PLCC-28 package supports standard through-hole or socket mounting for retrofit installations, while the 256 kHz maximum clock supports decimation ratios up to 256 for 1 kHz output rates. The fourth-order modulator maintains flat noise floor across the entire conversion range.
推荐
推荐产品汇总
工程参考数据： AD1555BPRL ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD1555APRL | AD1555BPZ | AD1556APZ |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-pin PLCC | 28-pin PLCC - same | 28-pin LCC (ceramic) | 28-pin PLCC - same |
| Resolution | 24-bit | 24-bit | 24-bit | 24-bit (digital filter) |
| Dynamic Range | 116 dB min / 120 dB typ | 115 dB min (slightly lower) | 116 dB min / 120 dB typ | N/A (filter only) |
| Max Sampling Rate | 256 kHz | 256 kHz | 256 kHz | Matches modulator clock |
| Integrated PGA | Yes (gain 1 to 128) | Yes (gain 1 to 128) | Yes (gain 1 to 128) | No (filter only) |
| Input-Referred Noise | 80 nV/√Hz | 85 nV/√Hz | 80 nV/√Hz | N/A |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
| Lifecycle Status | NRND | Obsolete | NRND | NRND |
关键差异点
- Integrated PGA with 1 to 128 gain range （对比 AD1556APZ)
- 120 dB typical dynamic range （对比 AD1555APRL)
- Fourth-order sigma-delta modulator with on-chip calibration （对比 AD1555BPZ)
设计说明
The AD1555BPRL requires ±5 V analog supplies (AVDD/AVSS) and a +3 V to +5 V digital supply (DVDD). According to the AD1555 datasheet, each supply pin requires 10 µF tantalum in parallel with 0.1 µF ceramic decoupling placed within 5 mm of the pin. Separate analog and digital ground planes tied at a single point under the IC prevent digital switching transients from coupling into the analog modulator, which is critical for achieving the rated 120 dB dynamic range.
Route the analog input traces (AIN+/AIN-) as a guarded differential pair with ground shielding to reject common-mode noise, especially at PGA gains > 1 where 80 nV/√Hz input noise can be dominated by board-induced pickup. Keep the bitstream output (BSOUT/BSOUT-2) traces away from the analog inputs by at least 5 mm or use a ground guard trace. The 28-pin PLCC land pattern should follow the JEDEC PLCC-28 standard with thermal relief spokes connecting to the analog ground pour.
Common design pitfalls when using the AD1555BPRL include: (1) omitting the AD1556 digital filter - the part is a modulator only and produces only a ones-density bitstream, not 24-bit words; (2) exceeding the PGA common-mode input range at high gains - check the differential input voltage against the AGND-centered input common-mode spec; (3) using single-ended analog inputs - differential drive is required for full THD performance; (4) ignoring clock jitter on MCLK - use a clean low-jitter oscillator to avoid reducing SNR.
合规信息
RoHS/REACH compliance not stated in the datasheet or verified web data; part is in PLCC-28 commercial package. Conflict-mineral compliance per company policy.
