AD9226ARSZ - 12-Bit 65 MSPS Pipeline ADC | Analog Devices
料号： AD9226ARSZ ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $30.1 | $3,010.00 |
| 500 | $26.75 | $13,375.00 |
| 1,000 | $23.4 | $23,400.00 |
AD9226ARSZ 概述
An analog-to-digital converter (ADC) is a data converter that transforms continuous analog signals into discrete digital codes for processing by DSPs, FPGAs, and microcontrollers. Pipeline ADCs like the AD9226 use multiple low-resolution flash stages to achieve high sample rates with low latency; they sit within the hierarchy of successive-approximation (SAR), delta-sigma, and flash ADCs, and belong to the broader data-converter family of mixed-signal ICs used in signal-chain and instrumentation systems.
Key features include a signal-to-noise ratio of approximately 69 dB, a spurious-free dynamic range (SFDR) of approximately 80 dB, an effective number of bits (ENOB) of 11.1 at fIN = 10 MHz, and a low-power architecture aimed at imaging and communications front-ends. The wideband sample-and-hold input supports differential or single-ended drive with simple passive or active signal conditioning, and the digital outputs provide CMOS-compatible parallel data.
Internally the AD9226 uses a multistage differential pipeline architecture with output error-correction logic. The on-chip 2.5 V reference can be left internal or overdriven by an external reference for gain calibration or channel matching in multi-board systems; the data-ready output simplifies interface to FIFOs, DSPs, and FPGAs.
Typical applications include medical ultrasound imaging, IF sampling in communications receivers, baseband digital signal processing, instrumentation digitizers, and CCD/camera imaging systems. The combination of 12-bit resolution, 65 MSPS sampling rate, and 28-SSOP footprint makes it a versatile front-end for mid-bandwidth data acquisition.
When designing with the AD9226, the most important consideration is using a single +5 V supply rail and providing proper analog input common-mode biasing; bypassing the supply pins with 100 nF and 10 uF ceramic capacitors placed within a few millimetres of each pin maintains rated dynamic performance and minimizes digital coupling into the analog front-end.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers shorten the selection and PCB procurement cycle.
直接替换替代料： AD9226ARSZ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： AD9226ARSZ （相同外形与封装尺寸） ——差异在于 Architecture, Input Type, Number of Channels, Operating Temperature, Package.
快速对比工具——选择替代料号进行并排对比：
AD9226ARS-REEL
✅ 直接替换📋 参考替代料（不在目录中）
AD9225ARS
✅ 直接替换📋 参考替代料（不在目录中）
AD9220AR
✅ 直接替换📋 参考替代料（不在目录中）
AD9221ARS
✅ 直接替换📋 参考替代料（不在目录中）
AD9223AR
✅ 直接替换📋 参考替代料（不在目录中）
AD9226ARSZ 最大额定值与电气特性
| 分辨率 | 12 bits |
| Number of Channels | 1 |
| 采样率 | 65 MSPS |
| Architecture | Pipelined |
| Input Type | Differential, single-ended compatible |
| 电源电压 | 4.75 V to 5.25 V (single +5 V) |
| Signal-to-Noise Ratio (SNR) | 69 dB (typical at fIN = 31 MHz) |
| Effective Number of Bits (ENOB) | 11.1 (typical at fIN = 10 MHz) |
| Spurious-Free Dynamic Range (SFDR) | 80 dB (typical at fIN = 31 MHz) |
| Intermodulation Distortion | -75 dBFS at fIN = 140 MHz |
| On-Chip Reference | 2.5 V internal (drivable externally) |
| Data Interface | CMOS parallel |
| Data Output Format | Straight binary, parallel |
| 工作温度 | -40 C to +85 C |
| 封装 | 28-SSOP (5.30 mm width) |
| Packaging Type | Tube |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
AD9226ARSZ 引脚配置
| 引脚 1 | CML — Common-mode level reference voltage output |
| 引脚 2 | DRVDD — Digital driver supply (5 V) |
| 引脚 3 | DGND — Digital ground |
| 引脚 4 | OE — Output enable, active high |
| 引脚 5 | NC — Not connected |
| 引脚 6 | D11 — Data output bit 11 (MSB) |
| 引脚 7 | D10 — Data output bit 10 |
| 引脚 8 | D9 — Data output bit 9 |
| 引脚 9 | D8 — Data output bit 8 |
| 引脚 10 | D7 — Data output bit 7 |
| 引脚 11 | D6 — Data output bit 6 |
| 引脚 12 | D5 — Data output bit 5 |
| 引脚 13 | D4 — Data output bit 4 |
| 引脚 14 | NC — Not connected |
| 引脚 15 | DRVDD — Digital driver supply (5 V) |
| 引脚 16 | DGND — Digital ground |
| 引脚 17 | DR — Data ready output strobe |
| 引脚 18 | DFS — Data format select (binary output indicator) |
| 引脚 19 | CLK — Clock encode input |
| 引脚 20 | AVDD — Analog supply (5 V) |
| 引脚 21 | AVSS — Analog ground |
| 引脚 22 | SENSE — Reference configuration input |
| 引脚 23 | VREF — Voltage reference (2.5 V internal) |
| 引脚 24 | CAPB — Reference decoupling capacitor B |
| 引脚 25 | CAPA — Reference decoupling capacitor A |
| 引脚 26 | VIN- — Analog differential input negative |
| 引脚 27 | VIN+ — Analog differential input positive |
| 引脚 28 | AVDD — Analog supply (5 V) |
典型应用
AD9226ARSZ 适用于 6 应用s: Medical Ultrasound Imaging Front-End, IF Sampling in Communications Receivers, Industrial Data-Acquisition Systems, CCD and CMOS Camera Imaging Digitizer, Radar and Lidar Signal Capture, Portable Test and Measurement Instrumentation.
Medical Ultrasound Imaging Front-End
The AD9226ARSZ's 12-bit resolution and 65 MSPS sampling rate make it ideal for the analog front-end of medical ultrasound beamformers that digitize received echoes from piezoelectric transducers. The 80 dB SFDR preserves contrast between small tissue reflections and large specular echoes, and the 69 dB SNR ensures clean grayscale rendering. Placed after a TGC amplifier and LNA at the receive chain, the ADC converts at 65 MSPS to satisfy 30 MHz probe bandwidth. A single +5 V rail simplifies medical-cart and handheld-device power trees with reinforced isolation.
推荐
IF Sampling in Communications Receivers
The AD9226ARSZ enables direct IF sampling in narrow-band base-station and software-defined-radio receivers by digitizing 10-70 MHz intermediate-frequency signals without a second down-conversion stage. Its 65 MSPS rate comfortably oversamples the IF bandwidth, while the pipelined core keeps latency low for receiver feedback paths. The 28-SSOP footprint supports multi-IF boards where each antenna branch carries one AD9226ARSZ paired with an RF front-end. Using the internal 2.5 V reference removes a calibration pass.
推荐
Industrial Data-Acquisition Systems
In factory-automation data-acquisition modules the AD9226ARSZ converts 0-5 V transducer signals such as vibration sensors, load cells, and process-control voltages into 12-bit digital codes. The 65 MSPS throughput allows multi-channel time-interleaved capture, while the 28-SSOP industrial-temperature (-40 to +85 C) grade supports cabinet installations. Each channel pairs the ADC with an instrumentation amplifier and an antialiasing filter, after which data is streamed to an FPGA over the parallel CMOS bus. RoHS compliance simplifies EU plant deployments.
推荐
CCD and CMOS Camera Imaging Digitizer
The AD9226ARSZ digitizes analog video from CCD image-sensor readout ASICs in industrial machine-vision and broadcast cameras. Its 65 MSPS rate supports progressive-scan 720p/1080i formats and higher-resolution preview modes, while the 12-bit resolution preserves tonal detail in shaded regions. Mounted adjacent to the analog video processor, the converter feeds a video encoder or an FPGA that performs on-camera image signal processing. Power dissipation near 300 mW is acceptable for enclosed camera housings with moderate airflow.
推荐
Radar and Lidar Signal Capture
The AD9226ARSZ is well matched to short-range automotive and industrial radar receivers where 12-bit accuracy and 65 MSPS sampling capture IF returns from FMCW chirp and pulsed LIDAR front-ends. The differential sample-and-hold input cancels common-mode noise from the antenna chain, and the 80 dB SFDR protects small return amplitudes against distortion. The 28-SSOP footprint supports multi-channel radar head-prints where one ADC is allocated per Rx antenna with tight channel-to-channel skew.
推荐
Portable Test and Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and bench digitizers benefit from the AD9226ARSZ's combination of 65 MSPS real-time sampling and a single +5 V supply. The 12-bit resolution supports 0.5% DC accuracy on the metrology front-end, and the on-chip 2.5 V reference reduces external components. The 28-SSOP footprint keeps the analog front-end small, so portable instruments can pack four AD9226 channels in a slim enclosure. The CMOS-parallel output simplifies connection to low-cost FPGAs implementing deep acquisition memory.
推荐
推荐产品汇总
工程参考数据： AD9226ARSZ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD9226ARS-REEL | AD9225ARS | AD9220AR |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 28-SSOP | 28-SSOP - same | 28-SSOP - same | 28-SSOP - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits |
| Sampling Rate | 65 MSPS | 65 MSPS | 25 MSPS | 10 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Supply Voltage | +5 V single | +5 V single | +5 V single | +5 V single |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| RoHS Status | Compliant | Compliant | Compliant | Compliant |
| Packaging | Tube | Tape & Reel | Tube | Tube |
关键差异点
- Best sample-rate headroom within the AD92xx 28-SSOP family （对比 AD9225ARS)
- Mid-range speed balanced against low power （对比 AD9220AR)
- Differential sample-and-hold input （对比 AD9226ARS-REEL)
设计说明
The AD9226ARSZ requires a clean +5 V rail because analog current spikes during sampling can couple noise from an unregulated supply into the AVDD pin and degrade SNR. Estimated: place a 10 uF tantalum and a 100 nF ceramic decoupling capacitor within 5 mm of each AVDD pin; a separate ferrite or pi-filter between the digital +5 V and analog +5 V reduces digital-rail noise. Allow 200 mV of headroom on the regulator to keep dropout margin.
Route the differential analog inputs (VIN+, VIN-) on a matched-impedance strip-line to balance skew and preserve SFDR; route them on the top layer above a continuous analog ground plane. Enclose encode-clock traces with their own guard ground and keep the CLK trace at least 3 line-widths from analog traces to limit coupling. Place CAPA and CAPB reference decoupling capacitors right at the IC to maintain reference stability over temperature.
Do not leave the SENSE pin floating - it must be strapped to AVDD or AGND per the AD9226 datasheet reference-configuration table to enable the on-chip 2.5 V reference. A floating SENSE pin puts the internal reference into a defined-but-untrimmed state and can produce up to 5% gain error. When the part is not used during power-down, drive OE high before power-down and verify the data outputs are not driving the FPGA inputs.
合规信息
RoHS compliant per Analog Devices product page. The 'Z' suffix designates Pb-free lead finish. Halogen-free status not stated in available data and should be confirmed with the manufacturer for specific applications.