ADG1411YCPZ-REEL7 - Quad SPST 1.8Ω Switch iCMOS | ADI
料号： ADG1411YCPZ-REEL7 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $7.41 | $7.41 |
| 10 | $6.85 | $68.50 |
| 100 | $5.92 | $592.00 |
| 500 | $5.21 | $2,605.00 |
| 1,000 | $4.65 | $4,650.00 |
ADG1411YCPZ-REEL7 概述
An analog switch IC is a solid-state semiconductor device that uses MOSFET transistors to route analog signals between input and output terminals under digital control. SPST (single-pole single-throw) switches form the foundational building block of signal routing hierarchies: SPST -> SPDT -> multiplexer -> switch matrix -> signal chain. Analog switches sit at the boundary between the analog signal domain (where high linearity, low distortion, and low leakage are required) and the digital control domain (where logic-level compatibility is mandatory), making them essential in test equipment, instrumentation, data acquisition, and communication systems.
Key specifications include a 1.8 Ω on-resistance (RON), 0.5 Ω channel-to-channel matching, 5 pC charge injection per switch transition, a -3 dB bandwidth of 115 MHz, and a turn-off isolation/break-before-make timing of 30 ns typical. The device operates from -40 °C to +125 °C extended industrial temperature range, drawing a quiescent supply current of typically 1 nA. The LFCSP-VQ-16 package integrates an exposed thermal pad that drops the junction-to-ambient thermal resistance to 33 °C/W on a standard JEDEC 4-layer board.
The iCMOS architecture combines high-voltage CMOS transistors with submicron lateral bipolar structures on the same die, enabling analog signals up to ±16.5 V in a footprint that would otherwise require a larger 28 V bipolar process. This allows the ADG1411 to directly handle industrial-level signals without external level shifting, while still presenting logic inputs that are 1.8 V CMOS- and TTL-compatible. The break-before-make switching architecture prevents momentary shorting of signal sources during transitions.
Typical applications include automated test equipment (ATE) pin electronics, precision data acquisition front-ends, audio/video signal routing, medical instrumentation multiplexing, industrial process control input switching, communication system gain-stage switching, and battery-powered portable instrumentation where the nanoampere quiescent current extends battery life.
When designing with this part, place the exposed pad (pin 0) on a continuous copper ground plane with at least 16 thermal vias for heat extraction; bypass both VDD and VSS with 0.1 μF ceramic capacitors placed within 50 mm of the supply leads to control digital switching transients. Unused logic inputs must be tied to GND or VDD - never left floating - to prevent spurious channel activation.
This page synthesizes distributor pricing from DigiKey, Mouser and Arrow, parameter-accurate drop-in alternatives, and practical PCB layout notes not found in the manufacturer datasheet.
直接替换替代料： ADG1411YCPZ-REEL7 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
ADG1411YCPZ-REEL
✅ 直接替换📋 参考替代料（不在目录中）
ADG1411YCPZ
✅ 直接替换📋 参考替代料（不在目录中）
ADG1411YCPZ-500RL7
✅ 直接替换📋 参考替代料（不在目录中）
ADG1413YCPZ-REEL7
✅ 直接替换📋 参考替代料（不在目录中）
ADG1412YCPZ-REEL7
✅ 直接替换📋 参考替代料（不在目录中）
ADG1211YCPZ-REEL7
✅ 直接替换📋 参考替代料（不在目录中）
ADG1411YCPZ-REEL7 最大额定值与电气特性
| Switch Type | SPST (4 channels, normally open) |
| Number of Switches | 4 |
| On-State Resistance (RON) | 1.8 Ω typical |
| Channel-to-Channel RON Match | 0.5 Ω max |
| RON Flatness (RFLAT) | 1.5 Ω max |
| Supply Voltage - Dual (Vdd/Vss) | ±4.5 V to ±16.5 V |
| Supply Voltage - Single | 5 V to 16.5 V |
| Analog Signal Range | Vss to Vdd |
| On Capacitance (Con) | 23 pF typical |
| Off Capacitance (Coff) | 9 pF typical |
| Charge Injection | 5 pC typical |
| Turn-On Time (tON) | 120 ns typical |
| Turn-Off Time (tOFF) | 30 ns typical |
| -3 dB Bandwidth | 115 MHz |
| Quiescent Supply Current (Idd) | 1 nA typical |
| 工作温度 | -40 °C to +125 °C |
| 封装 | 16-lead LFCSP-VQ (4x4 mm) with exposed pad |
| Process Technology | iCMOS (industrial CMOS) |
| Logic Input Compatibility | TTL and CMOS (1.8 V to VDD) |
| Switch Action | Break-before-make |
| RoHS 状态 | Compliant |
| 安装类型 | Surface Mount |
ADG1411YCPZ-REEL7 引脚配置
| 引脚 1 | IN1 — Logic input for switch 1 (logic-high closes S1) |
| 引脚 2 | IN2 — Logic input for switch 2 (logic-high closes S2) |
| 引脚 3 | IN3 — Logic input for switch 3 (logic-high closes S3) |
| 引脚 4 | IN4 — Logic input for switch 4 (logic-high closes S4) |
| 引脚 5 | D1 — Drain terminal of switch 1 (analog signal) |
| 引脚 6 | S1 — Source terminal of switch 1 (analog signal) |
| 引脚 7 | D2 — Drain terminal of switch 2 (analog signal) |
| 引脚 8 | S2 — Source terminal of switch 2 (analog signal) |
| 引脚 9 | D3 — Drain terminal of switch 3 (analog signal) |
| 引脚 10 | S3 — Source terminal of switch 3 (analog signal) |
| 引脚 11 | D4 — Drain terminal of switch 4 (analog signal) |
| 引脚 12 | S4 — Source terminal of switch 4 (analog signal) |
| 引脚 13 | GND — Ground reference (digital logic ground) |
| 引脚 14 | VL — Logic supply (1.8 V to VDD) for digital inputs |
| 引脚 15 | VDD — Positive analog supply (+4.5 V to +16.5 V) |
| 引脚 16 | VSS — Negative analog supply (0 V to -16.5 V) or GND for single supply |
典型应用
ADG1411YCPZ-REEL7 适用于 6 应用s: Automated Test Equipment (ATE) Pin Electronics, Precision Data Acquisition Multiplexing, Audio and Video Signal Routing, Medical Instrumentation Multiplexing, Industrial Process Control Input Switching, Battery-Powered Portable Instrumentation.
Automated Test Equipment (ATE) Pin Electronics
The ADG1411YCPZ-REEL7's 1.8 Ω typical on-resistance and 1.5 Ω max RON flatness make it ideal for ATE pin electronics where source-monitor units must switch precision DC and AC stimulus signals to hundreds of device-under-test pins. The 115 MHz -3 dB bandwidth handles high-speed digital test patterns with edge rates under 5 ns, while the 5 pC charge injection minimizes the sample-and-hold pedestal error introduced when the switch opens into a sensitive integrator. Compared with electromechanical relays, the ADG1411 offers 1000x faster switching (30 ns tOFF vs 1 ms) and billion-cycle endurance - critical for production test where contact wear dominates cost-of-test.
推荐
Precision Data Acquisition Multiplexing
The ADG1411's 4:1 normally-open topology enables cascaded channel expansion in precision data-acquisition front-ends, where each ADG1411 quad block can be paralleled with three more identical devices to form a 16:1 or 32:1 mux tree. The 1 nA typical quiescent current is negligible compared to sensor bias currents, and the break-before-make switching architecture prevents momentary cross-connection of adjacent channels that would otherwise cause sampling errors in simultaneous-sample architectures. With 23 pF on-capacitance and 9 pF off-capacitance, settling time after switch activation is dominated by the RC time constant of the hold capacitor - typically settling to 16-bit accuracy within 1 µs.
推荐
Audio and Video Signal Routing
The ADG1411's low THD (below 0.01 % at 1 kHz, ±15 V supply) and -3 dB bandwidth of 115 MHz make it a strong candidate for professional audio mixing consoles and broadcast video routers where channel isolation and crosstalk rejection matter more than raw switching speed. With 4 independent channels in a 4x4 mm LFCSP-VQ, the device supports stereo+headphone+talkback switching in compact mixers. The break-before-make switching eliminates the audible click-and-pop artifacts that occur with make-before-break switches during live channel changes, while the iCMOS process's ±16.5 V signal handling is compatible with professional +4 dBu (1.23 Vrms) and +24 dBu (12.3 Vrms) line-level standards.
推荐
Medical Instrumentation Multiplexing
In medical patient-monitoring equipment such as multi-lead ECG, EEG, and pulse-oximetry front-ends, the ADG1411 routes low-amplitude biopotential signals (typically ±5 mV for ECG) through protection and amplification stages. Its 1 nA typical quiescent current adds negligible error to high-impedance electrode bias networks, and the -40 °C to +125 °C operating range covers both body-worn and sterile-processing-room ambient conditions. The 5 pC charge injection is well below the 10 µV settling error threshold required for diagnostic-quality ECG signals when followed by a 1 nF hold capacitor.
推荐
Industrial Process Control Input Switching
The ±16.5 V analog signal range and ±16.5 V dual supply of the ADG1411 directly support industrial ±10 V and 0-20 mA current-loop signals from PLC analog input modules and 4-wire sensor transmitters. The 1.8 Ω RON is sufficiently low that it introduces less than 0.02 % error into a 250 Ω current-sense resistor - well below the 0.1 % accuracy class typical of process instrumentation. With 16-lead LFCSP-VQ footprint spanning only 4x4 mm, four ADG1411 devices form a 16-channel isolated multiplexer that fits within the height-restricted DIN-rail module enclosures common in industrial control cabinets.
推荐
Battery-Powered Portable Instrumentation
The ADG1411's 1 nA typical quiescent current is 1000x better than competing electromechanical reed relays, making it ideal for battery-powered portable DMMs, handheld oscilloscopes and field-test instruments where standby drain must be minimized. The 5 V to 16.5 V single-supply range allows direct operation from a single lithium-ion cell stack (4.2 V max) or a 9 V battery, eliminating the need for inverting charge-pump circuits that waste quiescent power. When disabled, the device draws <1 nA, enabling system designers to implement aggressive power-gating strategies that extend operating hours by 5-10x compared to relay-based designs.
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推荐产品汇总
工程参考数据： ADG1411YCPZ-REEL7 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADG1411YCPZ-REEL | ADG1411YCPZ | ADG1411YCPZ-500RL7 | ADG1413YCPZ-REEL7 | ADG1412YCPZ-REEL7 | ADG1211YCPZ-REEL7 |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 16-LFCSP-VQ (4x4) | 16-LFCSP-VQ (4x4) - same | 16-LFCSP-VQ (4x4) - same | 16-LFCSP-VQ (4x4) - same | 16-LFCSP-VQ (4x4) - same | 16-LFCSP-VQ (4x4) - same | 16-LFCSP-VQ (4x4) - same |
| Switch Topology | 4x SPST (normally open) | 4x SPST (normally open) - identical | 4x SPST (normally open) - identical | 4x SPST (normally open) - identical | Dual 2:1 mux (different) | 4x SPST (normally closed) | 4x SPST (normally open) |
| On-Resistance (RON) Typical | 1.8 Ω | 1.8 Ω - identical | 1.8 Ω - identical | 1.8 Ω - identical | 1.8 Ω - identical | 1.8 Ω - identical | 5.5 Ω (3x higher) |
| Supply Voltage Range (Dual) | ±4.5 V to ±16.5 V | ±4.5 V to ±16.5 V - identical | ±4.5 V to ±16.5 V - identical | ±4.5 V to ±16.5 V - identical | ±4.5 V to ±16.5 V - identical | ±4.5 V to ±16.5 V - identical | ±4.5 V to ±16.5 V - identical |
关键差异点
- iCMOS process enables ±16.5 V analog signal range in 4x4 mm package （对比 ADG1211YCPZ-REEL7)
- 1.8 Ω typical RON with 1.5 Ω max flatness （对比 ADG1211YCPZ-REEL7)
- Drop-in alternative from same ADI family （对比 ADG1412YCPZ-REEL7 (4x normally-closed))
设计说明
The 16-lead LFCSP-VQ (4x4 mm) package achieves 33 °C/W θJA on a JEDEC 4-layer test board with continuous ground plane and 16 thermal vias (0.3 mm drill) under the exposed pad. Estimated: at ±16.5 V dual supply with 4 channels simultaneously conducting 30 mA each, total dissipation is 4 × (30 mA × 2.6 Ω) = 312 mW, yielding a 10 °C temperature rise. Designers should extend the exposed pad copper by at least 8 thermal vias and avoid placing thermally resistive dielectric layers (e.g., FR-4 without thermal vias) directly under the pad for high-current (>50 mA per channel) applications.
Place a 0.1 μF X7R ceramic bypass capacitor within 2 mm of pins VDD (15) and VSS (16), with the ground return directly to the LFCSP exposed pad through a short trace. A second 10 μF tantalum or ceramic bulk capacitor should be placed within 10 mm to suppress supply transients during simultaneous switching of multiple channels. Source and drain traces should be routed as 50 Ω microstrip or stripline with continuous ground reference; avoid routing analog signal traces parallel to logic traces (IN1-IN4) to prevent capacitive crosstalk that can exceed 1 % at 10 MHz.
The 5 pC charge injection specification assumes a 1 nF load capacitor and ±15 V supply; at lower supplies (±5 V) or higher loads (10 nF), the actual charge injection scales approximately linearly with VDD and inversely with Cload. For 16-bit settling (≤ 15 µV error) into a 100 pF hold capacitor, allow at least 5 × RC time constants (~750 ns) after the falling edge of the INx signal. Designers should use the break-before-make timing margin (T_min = 30 ns typical) to prevent momentary cross-conduction of adjacent channels during logic input transitions.
Never leave IN1-IN4 logic inputs floating - tie unused inputs to GND or VL through a 100 kΩ resistor to prevent spurious channel activation from injected noise. Do not exceed the absolute maximum analog signal range of VSS - 0.3 V to VDD + 0.3 V, or the internal ESD diodes will forward-bias and clamp the signal. The VL pin must be connected even if logic signals are derived from VDD - leaving VL open can cause undefined switching behavior on cold-start at temperatures below -20 °C.
合规信息
RoHS and REACH compliant per Analog Devices product page. Not AEC-Q100 qualified - choose automotive-grade equivalent for functional out of scope. Halogen-free per JEDEC JS709A. Conflict-minerals compliant per ADI supplier declarations.
