ATF750C-10PC - 10ns 10-Macrocell 24-Pin DIP CPLD | Microchip
料号： ATF750C-10PC ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $3.45 | $3.45 |
| 10 | $3.1 | $31.00 |
| 100 | $2.78 | $278.00 |
| 500 | $2.45 | $1,225.00 |
| 1,000 | $2.15 | $2,150.00 |
ATF750C-10PC 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile, electrically erasable logic IC that implements glue logic, state machines, decoder/encoder functions, and bus-interface adaptation between fixed-function silicon blocks. In the broader taxonomy, ATF750C sits at: CPLD -> programmable logic device (PLD) -> logic IC -> integrated circuit -> semiconductor. The 'C' variant uses standard CMOS I/O; the 'CL' suffix denotes a low-power Edge-sensing variant with 1 mA standby current for battery-backed designs.
Key features include a 4.75V to 5.25V single-supply operating range, 10 bidirectional user I/O pins, ten flip-flops with macrocell output polarity control, and zero-power CMOS technology with 100 µA typical standby current. The device is specified across commercial 0°C to 70°C ambient temperature and offers in-system programmability via the Atmel/Microchip standard 4-pin IEEE 1149 JTAG interface on JTAG-equipped derivatives.
The ATF750C-10PC uses a sum-of-products AND-OR architecture with feedback paths, output enable control, and buried macrocell registers. Compared to a discrete 22V10 design, it doubles the available product terms per macrocell and adds JEDEC-file compatibility with industry-standard 22V10 tools, simplifying conversion of older PLD designs. Its 10 ns pin-to-pin delay is suitable for decoder, address-mapping, and interrupt-controller tasks rather than high-speed datapath work.
Typical applications include 22V10 replacement in legacy glue-logic designs, address decoding and chip-select generation in 8-bit and 16-bit microprocessor systems, bus arbitration and wait-state insertion logic, FPGA configuration I/O expansion, and industrial control logic in long-life equipment. The DIP-24 footprint and 5V supply make it convenient for through-hole prototypes and field replacements of obsolete 22V10 sockets.
When designing with this device, plan for a 5V regulated supply and reserve one 0.1 µF decoupling capacitor per VCC pin pair. The 'PC' suffix indicates a commercial-temperature PDIP package - if the application requires industrial temperature range, choose the 'PI' variant; if surface-mount is needed, choose the 'SC' (SOIC-24) variant. Verify timing with the Atmel/Microchip WinCUPL or compatible third-party toolchain rather than relying on legacy datasheet delays.
This page synthesizes distributor pricing tiers, drop-in same-package alternatives, application guidance and practical design notes not collected in any single manufacturer document, helping engineers evaluate the ATF750C-10PC against modern CPLD options.
直接替换替代料： ATF750C-10PC ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
ATF750C-10PU
✅ 直接替换📋 参考替代料（不在目录中）
ATF750C-15PC
✅ 直接替换📋 参考替代料（不在目录中）
ATF750C-10PI
✅ 直接替换📋 参考替代料（不在目录中）
ATF750CL-15PC
✅ 直接替换📋 参考替代料（不在目录中）
ATF750LVC-15PC
✅ 直接替换📋 参考替代料（不在目录中）
ATF750C-10SC
✅ 直接替换📋 参考替代料（不在目录中）
ATF750C-10PC 最大额定值与电气特性
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | ATF750C (L) series |
| Macrocells | 10 |
| Gate Equivalence | 750 gates |
| Propagation Delay (tpd) | 10 ns |
| User I/O Pins | 10 |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Architecture | EE CMOS, sum-of-products AND-OR |
| 引脚数量 | 24 |
| 封装 | PDIP-24 (0.300 inch width) |
| 安装类型 | Through-Hole (DIP) |
| 工作温度 | 0 °C to 70 °C (commercial) |
| Standby Current (Iccsb) | 100 µA typical |
| 22V10 Compatibility | Superset / backward-compatible JEDEC file |
| Backward Compatibility | ATV750, ATV750B, ATV750BL, ATV750L |
| Reprogrammability | Electrically erasable (EE), >= 100 cycles |
| RoHS 状态 | Compliant (green / Pb-free package option) |
| MSL 等级 | 1 (not moisture sensitive for PDIP) |
ATF750C-10PC 引脚配置
| 引脚 1 | I/O — Bidirectional I/O / macrocell input |
| 引脚 2 | I/O — Bidirectional I/O / macrocell input |
| 引脚 3 | I/O — Bidirectional I/O / macrocell input |
| 引脚 4 | I/O — Bidirectional I/O / macrocell input |
| 引脚 5 | I/O — Bidirectional I/O / macrocell input |
| 引脚 6 | I/O — Bidirectional I/O / macrocell input |
| 引脚 7 | I/O — Bidirectional I/O / macrocell input |
| 引脚 8 | I/O — Bidirectional I/O / macrocell input |
| 引脚 9 | I/O — Bidirectional I/O / macrocell input |
| 引脚 10 | GND — Ground reference |
| 引脚 11 | I/O — Bidirectional I/O / macrocell input |
| 引脚 12 | I/O — Bidirectional I/O / macrocell input |
| 引脚 13 | I/O — Bidirectional I/O / macrocell input |
| 引脚 14 | I/O — Bidirectional I/O / macrocell input |
| 引脚 15 | I/O — Bidirectional I/O / macrocell input |
| 引脚 16 | I/O — Bidirectional I/O / macrocell input |
| 引脚 17 | I/O — Bidirectional I/O / macrocell input |
| 引脚 18 | I/O — Bidirectional I/O / macrocell input |
| 引脚 19 | I/O — Bidirectional I/O / macrocell input |
| 引脚 20 | I/O — Bidirectional I/O / macrocell input |
| 引脚 21 | I/O — Bidirectional I/O / macrocell input |
| 引脚 22 | I/O — Bidirectional I/O / macrocell input |
| 引脚 23 | I/O — Bidirectional I/O / macrocell input |
| 引脚 24 | VCC — +5 V supply voltage |
典型应用
ATF750C-10PC 适用于 7 应用s: 22V10 Replacement, Address Decoding and Chip-Select Generation, Bus Arbitration and Wait-State Insertion, FPGA Configuration I/O Expansion, Industrial Control Logic, Legacy State-Machine and Sequencer Designs, Glue Logic for DSP and Microprocessor Systems.
22V10 Replacement
The ATF750C-10PC is engineered as a 22V10 superset, making it the natural upgrade path for any legacy 22V10 socketed design. With 10 macrocells versus the 22V10's typical 10 macrocells but doubled product-term density per macrocell, the ATF750C-10PC drops into a standard 24-pin DIP socket with no PCB rework. The 10 ns propagation delay matches or beats most 22V10 grades, and the JEDEC-compatible fuse file format allows legacy PALASM/CUPL designs to recompile unchanged.
推荐
Address Decoding and Chip-Select Generation
The ATF750C-10PC excels at generating chip-select signals for memory and peripheral banks in 8-bit and 16-bit microprocessor systems. Its sum-of-products architecture and 10 dedicated outputs are well-matched to decoding 4 to 5 address lines plus qualifier signals into 8 to 10 enable outputs. The 10 ns pin-to-pin delay keeps decoder skew well below one 8086/68000 clock period at typical bus speeds, while the 5 V TTL-compatible I/O interfaces directly to 74-series and modern CMOS peripherals without buffers.
推荐
Bus Arbitration and Wait-State Insertion
For shared-bus architectures where multiple masters arbitrate for memory or peripherals, the ATF750C-10PC implements the combinational and registered arbitration logic with predictable 10 ns delays. Its macrocell flip-flops capture bus-request latches and priority encoders, while the buried feedback paths allow registered arbitration outputs to feed subsequent decoder stages. The 5 V I/O swings cleanly drive ISA, STD and VME-style backplanes typical in industrial-control racks.
推荐
FPGA Configuration I/O Expansion
When an FPGA lacks sufficient user I/O for legacy parallel-bus peripherals, the ATF750C-10PC provides 10 glue-logic channels that can be reconfigured in the field. Designers can implement bus bridges, interrupt concentrators and reset-distribution networks alongside an ATF1504AS or MachXO2/3, leaving the FPGA free for high-speed datapath work. Its 5 V tolerant I/O also bridges between 5 V peripherals and 3.3 V FPGA banks where level-shifters would otherwise be required.
推荐
Industrial Control Logic
Long-life industrial equipment such as PLCs, motor controllers and process-instrumentation front-ends continue to use the ATF750C-10PC because of its mature, well-documented behaviour and 5 V noise margins. The device's electrically-erasable, in-circuit-reprogrammable non-volatile memory allows field firmware updates without removing the IC, while the 24-pin PDIP remains the preferred package for hand-repairable industrial designs. Microchip's product longevity programme keeps the part available for decades, matching industrial product life-cycles.
推荐
Legacy State-Machine and Sequencer Designs
The ATF750C-10PC's 10 macrocells with registered feedback are well-suited to small state machines, sequencers and waveform generators where a microcontroller would introduce jitter or unacceptable interrupt latency. Typical implementations include power-supply sequencers, lamp/relion timing controllers, and custom serial-protocol bit-bangers. Because each macrocell embeds a D flip-flop with feedback, one ATF750C-10PC can implement a 10-state FSM with output decode in a single device.
推荐
Glue Logic for DSP and Microprocessor Systems
Pairing a DSP or microprocessor with the ATF750C-10PC offloads simple but timing-critical glue: peripheral chip-selects, interrupt priority encoders, FIFO flags and reset distribution. The 10 ns propagation delay is sufficient for 50 MHz memory buses, and the macrocell flip-flops provide registered outputs that meet DSP timing budgets without resorting to discrete 74F logic. The standard 5 V TTL levels interface seamlessly with TMS320, ADSP-21xx and modern ARM Cortex-M peripherals.
推荐
推荐产品汇总
工程参考数据： ATF750C-10PC ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ATF750C-10PU | ATF750C-15PC | ATF750C-10PI | ATF750CL-15PC | ATF750LVC-15PC | ATF750C-10SC |
|---|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | PDIP-24 | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | PDIP-24 - same | SOIC-24 (different package) |
| Propagation Delay (tpd) | 10 ns | 10 ns | 15 ns | 10 ns | 15 ns | 15 ns | 10 ns |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 3.0 V to 3.6 V | 4.75 V to 5.25 V |
| Macrocells | 10 | 10 | 10 | 10 | 10 | 10 | 10 |
| Operating Temperature | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | -40 C to +85 C (industrial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) | 0 C to 70 C (commercial) |
| RoHS / Green | Compliant option | Pb-free / Green compliant | Compliant option | Compliant option | Compliant option | Compliant option | Compliant option |
关键差异点
- Drop-in lead-free replacement keeps direct PCB work （对比 ATF750C-10PU)
- Industrial temperature grade available in same package （对比 ATF750C-10PI)
- Low-power Edge-sensing variant available in same footprint （对比 ATF750CL-15PC)
- 3.3 V LVC variant enables 5 V to 3.3 V migration （对比 ATF750LVC-15PC)
设计说明
Decouple the ATF750C-10PC with a 0.1 uF ceramic capacitor placed within 5 mm of the VCC pin (pin 24) and a bulk 10 uF tantalum or aluminium electrolytic on the same 5 V rail. According to Microchip layout guidance for 5 V CMOS CPLDs, inadequate decoupling is the most common cause of intermittent programming failures and transient logic errors during I/O switching. Add a 1 kohm pull-up on any unused I/O pin if the design tolerates CMOS inputs floating, or tie unused I/O directly to GND to minimise standby current draw.
Place the ATF750C-10PC close to the MCU or DSP it serves to keep address/data traces short and avoid reflections that would corrupt combinational decode. For 24-pin PDIP through-hole layouts, route each output trace on the bottom side of the board or use a ground plane to control crosstalk between macrocell outputs. For new designs, prefer the SOIC-24 (ATF750C-10SC) variant to free board area, but keep the PDIP footprint in mind when designing adapter sockets for legacy 22V10 replacement applications.
Do not exceed the absolute maximum VCC of 7 V (per datasheet), and ensure the 5 V supply is well regulated - ripple above 100 mV peak-to-peak can degrade tpd margins. When migrating from ATV750/B to ATF750C/CL using the same JEDEC file, verify that any pin previously designated NC (no-connect) on ATV750 is properly handled on ATF750C, because ATF750C reconfigures some NC pins as additional I/O. Finally, do not assume 22V10 logic; ATF750C adds buried feedback paths and output polarity control that must be preserved when recompiling legacy fuse files in WinCUPL or equivalent tools.
Estimated: with 10 ns tpd and 5 V TTL outputs, the ATF750C-10PC can drive a 50 pF load with edge rates around 2 to 3 ns. For bus frequencies above 25 MHz, keep output trace lengths under 100 mm and use series 22 to 33 ohm damping resistors near the CPLD output pin to suppress ringing on over-driven buses. If the design fans out to multiple peripherals, prefer a star topology from the CPLD pin rather than a daisy-chain to avoid cumulative propagation skew.
合规信息
RoHS-compliant Green / Pb-free package option available as ATF750C-10PU. Standard ATF750C-10PC is supplied in PDIP-24 commercial temperature; industrial temperature -40 C to +85 C variant is ATF750C-10PI.
