ATSAM3U4EA-AU - 96MHz Cortex-M3 MCU 256KB Flash | Microchip
料号： ATSAM3U4EA-AU ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $12.45 | $12.45 |
| 10 | $11.21 | $112.10 |
| 100 | $9.65 | $965.00 |
| 500 | $8.42 | $4,210.00 |
| 1,000 | $7.18 | $7,180.00 |
ATSAM3U4EA-AU 概述
A microcontroller (MCU) is a single-chip embedded processor that integrates a CPU core, program memory, data memory, and peripherals (UART, SPI, I2C, timers, USB, ADC) onto one die. In the embedded processing hierarchy, the SAM3U4E sits between entry-level Cortex-M0 MCUs and higher-performance Cortex-M4 parts, with Cortex-M3 being its 32-bit RISC core architecture. The Cortex-M3 revision 2.0 runs at up to 96 MHz, executes the Thumb-2 instruction set, and includes a Memory Protection Unit (MPU) for memory isolation and OS-style privilege separation. Hypernym chain: SAM3U4E -> SAM3U family -> ARM Cortex-M3 MCU -> 32-bit microcontroller -> embedded processor -> integrated circuit.
Key features include 256 KB of Flash accessed 128 bits wide through a memory accelerator that sustains near-zero wait-state execution from SRAM or Flash at full clock. The dual-bank architecture supports safe in-application programming (IAP) and firmware field updates without halting user code. A multi-layer AHB bus matrix, dedicated DMA channels, and Peripheral DMA Controllers (PDC) maximize concurrent peripheral throughput, while a high-speed USB 2.0 Full-Speed Device port with on-chip PHY targets USB data-acquisition designs.
The architecture sustains high-speed peripheral transfers by allowing parallel bus-matrix transactions between the Cortex-M3 core, SRAM banks, USB, and DMA engines. This makes the device well suited to USB data-acquisition dongles, industrial gateways, and test-instrument front ends where deterministic throughput matters more than raw compute.
Typical applications include USB data-acquisition modules, industrial control gateways, smart metering, point-of-sale terminals, and motor-control human-machine interface (HMI) panels. The 144-pin LQFP exposes up to four UART, three SPI, two I2C, USB, CAN, and a 12-bit ADC. Supply voltage spans 1.62V to 3.6V across the industrial temperature range -40C to +85C.
Design consideration: at 96 MHz place at least one 100 nF decoupling cap per supply pin, keep the ground plane unbroken, and use the flash accelerator with zero wait-state Flash configuration; if execution timing is critical, copy hot routines to SRAM.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet.
直接替换替代料： ATSAM3U4EA-AU ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ATSAM3U4EA-AU （相同外形与封装尺寸） ——差异在于 Core Architecture, Operating Temperature, Package, SRAM, Mounting Type.
快速对比工具——选择替代料号进行并排对比：
ATSAM3U4EA-AUR
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ATSAM3U4EA-CU
✅ 直接替换✓ 有现货
$12.05 / 个
查看数据手册 →ATSAM3U2EA-AU
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$7.22 / 个
查看数据手册 →ATSAM3U1EA-AU
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ATSAM3U4EA-AU 最大额定值与电气特性
| Core Architecture | ARM Cortex-M3 revision 2.0 |
| Maximum Clock Speed | 96 MHz |
| Instruction Set | Thumb-2 |
| Flash Memory | 256 KB (dual-bank, 128-bit wide access) |
| SRAM | 52 KB |
| Memory Protection Unit | Yes (MPU) |
| 电源电压 | 1.62 V to 3.6 V |
| 工作温度 | -40 C to +85 C (industrial) |
| 封装 | 144-pin LQFP (20x20 mm), surface mount |
| 安装类型 | Surface Mount |
| USB | USB 2.0 Full-Speed Device with on-chip PHY |
| CAN | Yes |
| MSL 等级 | 3 (168 hours) |
| RoHS 状态 | Compliant |
| Lead-Free | Yes |
ATSAM3U4EA-AU 引脚配置
| 引脚 1 | PB0 — GPIO port B, bit 0 |
| 引脚 2 | PB1 — GPIO port B, bit 1 |
| 引脚 3 | PB2 — GPIO port B, bit 2 |
| 引脚 4 | PB3 — GPIO port B, bit 3 |
| 引脚 5 | VDDOUT1 — Voltage regulator output |
| 引脚 6 | VDDIN1 — Voltage regulator input |
| 引脚 7 | VDDIO1 — I/O supply voltage 1 |
| 引脚 8 | GND — Ground |
| 引脚 9 | PB4 — GPIO port B, bit 4 |
| 引脚 10 | PB5 — GPIO port B, bit 5 |
| 引脚 11 | PB6 — GPIO port B, bit 6 |
| 引脚 12 | PB7 — GPIO port B, bit 7 |
| 引脚 13 | PB8 — GPIO port B, bit 8 |
| 引脚 14 | PB9 — GPIO port B, bit 9 |
| 引脚 15 | PB10 — GPIO port B, bit 10 |
| 引脚 16 | PB11 — GPIO port B, bit 11 |
| 引脚 17 | PB12 — GPIO port B, bit 12 |
| 引脚 18 | PB13 — GPIO port B, bit 13 |
| 引脚 19 | PB14 — GPIO port B, bit 14 |
| 引脚 20 | GND — Ground |
| 引脚 21 | PC0 — GPIO port C, bit 0 |
| 引脚 22 | PC1 — GPIO port C, bit 1 |
| 引脚 23 | PC2 — GPIO port C, bit 2 |
| 引脚 24 | PC3 — GPIO port C, bit 3 |
| 引脚 25 | PC4 — GPIO port C, bit 4 |
| 引脚 26 | PC5 — GPIO port C, bit 5 |
| 引脚 27 | PC6 — GPIO port C, bit 6 |
| 引脚 28 | PC7 — GPIO port C, bit 7 |
| 引脚 29 | PC8 — GPIO port C, bit 8 |
| 引脚 30 | PC9 — GPIO port C, bit 9 |
| 引脚 31 | PC10 — GPIO port C, bit 10 |
| 引脚 32 | PC11 — GPIO port C, bit 11 |
| 引脚 33 | PC12 — GPIO port C, bit 12 |
| 引脚 34 | GND — Ground |
| 引脚 35 | PA0 — GPIO port A, bit 0 |
| 引脚 36 | PA1 — GPIO port A, bit 1 |
| 引脚 37 | PA2 — GPIO port A, bit 2 |
| 引脚 38 | PA3 — GPIO port A, bit 3 |
| 引脚 39 | PA4 — GPIO port A, bit 4 |
| 引脚 40 | PA5 — GPIO port A, bit 5 |
| 引脚 41 | PA6 — GPIO port A, bit 6 |
| 引脚 42 | PA7 — GPIO port A, bit 7 |
| 引脚 43 | PA8 — GPIO port A, bit 8 |
| 引脚 44 | PA9 — GPIO port A, bit 9 |
| 引脚 45 | PA10 — GPIO port A, bit 10 |
| 引脚 46 | PA11 — GPIO port A, bit 11 / USB D- |
| 引脚 47 | PA12 — GPIO port A, bit 12 / USB D+ |
| 引脚 48 | PA13 — GPIO port A, bit 13 |
| 引脚 49 | PA14 — GPIO port A, bit 14 |
| 引脚 50 | PA15 — GPIO port A, bit 15 |
| 引脚 51 | GND — Ground |
| 引脚 52 | PA16 — GPIO port A, bit 16 |
| 引脚 53 | PA17 — GPIO port A, bit 17 |
| 引脚 54 | PA18 — GPIO port A, bit 18 |
| 引脚 55 | PA19 — GPIO port A, bit 19 |
| 引脚 56 | PA20 — GPIO port A, bit 20 |
| 引脚 57 | PA21 — GPIO port A, bit 21 |
| 引脚 58 | PA22 — GPIO port A, bit 22 |
| 引脚 59 | PA23 — GPIO port A, bit 23 |
| 引脚 60 | PA24 — GPIO port A, bit 24 |
| 引脚 61 | PA25 — GPIO port A, bit 25 |
| 引脚 62 | PA26 — GPIO port A, bit 26 |
| 引脚 63 | PA27 — GPIO port A, bit 27 |
| 引脚 64 | PA28 — GPIO port A, bit 28 |
| 引脚 65 | PA29 — GPIO port A, bit 29 |
| 引脚 66 | PA30 — GPIO port A, bit 30 |
| 引脚 67 | PA31 — GPIO port A, bit 31 |
| 引脚 68 | GND — Ground |
| 引脚 69 | VDDIO2 — I/O supply voltage 2 |
| 引脚 70 | NRST — Reset input, active low |
| 引脚 71 | TDI — JTAG Test Data In |
| 引脚 72 | TDO — JTAG Test Data Out |
| 引脚 73 | TMS — JTAG Test Mode Select |
| 引脚 74 | TCK — JTAG Test Clock |
| 引脚 75 | VDDIO2 — I/O supply voltage 2 |
| 引脚 76 | ERASE — Flash erase / test mode pin |
| 引脚 77 | GND — Ground |
| 引脚 78 | VDDIO3 — I/O supply voltage 3 |
| 引脚 79 | VDDIN2 — Voltage regulator input 2 |
| 引脚 80 | VDDOUT2 — Voltage regulator output 2 |
| 引脚 81 | GND — Ground |
| 引脚 82 | XIN — Crystal oscillator input |
| 引脚 83 | XOUT — Crystal oscillator output |
| 引脚 84 | GND — Ground |
| 引脚 85 | VDDCORE — Core supply voltage |
| 引脚 86 | VDDIO3 — I/O supply voltage 3 |
| 引脚 87 | GND — Ground |
| 引脚 88 | PA0 — GPIO port A, bit 0 (alt) |
| 引脚 89 | PA1 — GPIO port A, bit 1 (alt) |
| 引脚 90 | PA2 — GPIO port A, bit 2 (alt) |
| 引脚 91 | PA3 — GPIO port A, bit 3 (alt) |
| 引脚 92 | PA4 — GPIO port A, bit 4 (alt) |
| 引脚 93 | PA5 — GPIO port A, bit 5 (alt) |
| 引脚 94 | PA6 — GPIO port A, bit 6 (alt) |
| 引脚 95 | PA7 — GPIO port A, bit 7 (alt) |
| 引脚 96 | PA8 — GPIO port A, bit 8 (alt) |
| 引脚 97 | PA9 — GPIO port A, bit 9 (alt) |
| 引脚 98 | PA10 — GPIO port A, bit 10 (alt) |
| 引脚 99 | PA11 — GPIO port A, bit 11 (alt) |
| 引脚 100 | PA12 — GPIO port A, bit 12 (alt) |
| 引脚 101 | PA13 — GPIO port A, bit 13 (alt) |
| 引脚 102 | PA14 — GPIO port A, bit 14 (alt) |
| 引脚 103 | PA15 — GPIO port A, bit 15 (alt) |
| 引脚 104 | GND — Ground |
| 引脚 105 | VDDCORE — Core supply voltage |
| 引脚 106 | VDDIO4 — I/O supply voltage 4 |
| 引脚 107 | GND — Ground |
| 引脚 108 | PB0 — GPIO port B, bit 0 (alt) |
| 引脚 109 | PB1 — GPIO port B, bit 1 (alt) |
| 引脚 110 | PB2 — GPIO port B, bit 2 (alt) |
| 引脚 111 | PB3 — GPIO port B, bit 3 (alt) |
| 引脚 112 | PB4 — GPIO port B, bit 4 (alt) |
| 引脚 113 | PB5 — GPIO port B, bit 5 (alt) |
| 引脚 114 | PB6 — GPIO port B, bit 6 (alt) |
| 引脚 115 | PB7 — GPIO port B, bit 7 (alt) |
| 引脚 116 | PB8 — GPIO port B, bit 8 (alt) |
| 引脚 117 | PB9 — GPIO port B, bit 9 (alt) |
| 引脚 118 | PB10 — GPIO port B, bit 10 (alt) |
| 引脚 119 | PB11 — GPIO port B, bit 11 (alt) |
| 引脚 120 | PB12 — GPIO port B, bit 12 (alt) |
| 引脚 121 | PB13 — GPIO port B, bit 13 (alt) |
| 引脚 122 | PB14 — GPIO port B, bit 14 (alt) |
| 引脚 123 | GND — Ground |
| 引脚 124 | VDDCORE — Core supply voltage |
| 引脚 125 | PC0 — GPIO port C, bit 0 (alt) |
| 引脚 126 | PC1 — GPIO port C, bit 1 (alt) |
| 引脚 127 | PC2 — GPIO port C, bit 2 (alt) |
| 引脚 128 | PC3 — GPIO port C, bit 3 (alt) |
| 引脚 129 | PC4 — GPIO port C, bit 4 (alt) |
| 引脚 130 | PC5 — GPIO port C, bit 5 (alt) |
| 引脚 131 | PC6 — GPIO port C, bit 6 (alt) |
| 引脚 132 | PC7 — GPIO port C, bit 7 (alt) |
| 引脚 133 | PC8 — GPIO port C, bit 8 (alt) |
| 引脚 134 | PC9 — GPIO port C, bit 9 (alt) |
| 引脚 135 | PC10 — GPIO port C, bit 10 (alt) |
| 引脚 136 | PC11 — GPIO port C, bit 11 (alt) |
| 引脚 137 | PC12 — GPIO port C, bit 12 (alt) |
| 引脚 138 | GND — Ground |
| 引脚 139 | VDDIO5 — I/O supply voltage 5 |
| 引脚 140 | GND — Ground |
| 引脚 141 | DDP — USB D+ pad |
| 引脚 142 | DDM — USB D- pad |
| 引脚 143 | VDDUSB — USB transceiver supply |
| 引脚 144 | VDDIO5 — I/O supply voltage 5 |
典型应用
ATSAM3U4EA-AU 适用于 6 应用s: USB Data-Acquisition Dongle, Industrial Control Gateway, Smart Metering Endpoints, POS Terminals and Payment Peripherals, Motor-Control HMI Panels, Test and Measurement Front-End.
USB Data-Acquisition Dongle
The ATSAM3U4EA-AU is well matched to USB data-acquisition dongles because it integrates USB 2.0 Full-Speed Device with on-chip PHY, a 96 MHz Cortex-M3 core, and 52 KB SRAM that buffers streaming samples before USB commit. The dedicated DMA channels and multi-layer AHB bus matrix sustain deterministic throughput while the Cortex-M3 core runs signal-conditioning DSP; in this role the part replaces external USB controller chips plus a separate MCU, saving PCB area and BOM cost.
推荐
Industrial Control Gateway
For industrial control gateways the ATSAM3U4EA-AU delivers four UART, two I2C, three SPI, and CAN interfaces that bridge RS-485 sensors, Modbus nodes, and CAN-bus field devices to a backhaul link. The 1.62V-3.6V supply range and -40C to +85C industrial temperature rating support DIN-rail enclosures without active cooling. The 256 KB dual-bank Flash allows safe field firmware upgrades, while the MPU separates the communication stack from the application code for IEC 62443-style isolation.
推荐
Smart Metering Endpoints
Smart metering endpoints use the ATSAM3U4EA-AU for its low active power profile and multiple serial interfaces that link to metering AFE chips over SPI or UART. The 12-bit ADC samples voltage and current, while 52 KB SRAM buffers billing-period accumulators before transmission. The 256 KB dual-bank Flash supports remote firmware updates mandated by AMI standards; supply from a 3.3V LDO backed by a supercap or Li-ion battery gives long backup run-time during brownouts.
推荐
POS Terminals and Payment Peripherals
POS terminals leverage the ATSAM3U4EA-AU's USB Full-Speed Device for tethered card-reader dongles and serial peripherals for printer and cash-drawer control. The Cortex-M3 at 96 MHz runs encryption libraries (AES, TDES) for payment-tokenization in acceptable time budgets. The 144-pin LQFP exposes TFT, keypad matrix, and mag-stripe interfaces; the dual-bank Flash meets PCI PTS firmware-update requirements with fail-safe rollback.
推荐
Motor-Control HMI Panels
Motor-control HMI panels use the ATSAM3U4EA-AU to drive character or small graphic LCDs, scan keypads, and bridge to a host controller via UART, SPI, or CAN. The 12-bit ADC reads analog potentiometers or current sense, while PWM outputs drive status LEDs and buzzer tones. The industrial temperature rating tolerates factory-cabinet environments, and the bus matrix keeps display refresh independent of CAN traffic for a flicker-free UI.
推荐
Test and Measurement Front-End
Test-and-measurement front-ends use the ATSAM3U4EA-AU as a data aggregator for ADC samples streamed over USB to a host PC. The 96 MHz core and DMA channels sustain sample rates suitable for low-bandwidth oscilloscope or data-logger channels, while 52 KB SRAM doubles as a circular buffer. The dual-bank Flash allows field-upgrade of the FPGA or sensor interface; USB-FS removes the need for a dedicated USB bridge IC.
推荐
推荐产品汇总
工程参考数据： ATSAM3U4EA-AU ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ATSAM3U4EA-AUR | ATSAM3U4EA-CU | ATSAM3U2EA-AU |
|---|---|---|---|---|
| Package | LQFP-144 (20x20 mm) | LQFP-144 (20x20 mm) - same | LQFP-144 (20x20 mm) - same | LQFP-144 (20x20 mm) - same |
| Brand | Microchip Technology | Microchip Technology - same | Microchip Technology - same | Microchip Technology - same |
| Core | ARM Cortex-M3 rev 2.0 | ARM Cortex-M3 rev 2.0 - same | ARM Cortex-M3 rev 2.0 - same | ARM Cortex-M3 rev 2.0 - same |
| Maximum Clock | 96 MHz | 96 MHz - same | 96 MHz - same | 96 MHz - same |
| Flash Memory | 256 KB dual-bank | 256 KB dual-bank - same | 256 KB dual-bank - same | 128 KB dual-bank (-50%) |
| SRAM | 52 KB | 52 KB - same | 52 KB - same | 36 KB (-31%) |
| USB | USB 2.0 Full-Speed Device | USB 2.0 Full-Speed Device - same | USB 2.0 Full-Speed Device - same | USB 2.0 Full-Speed Device - same |
| Temperature Grade | Industrial -40C to +85C | Industrial -40C to +85C - same | Industrial -40C to +85C - same | Industrial -40C to +85C - same |
关键差异点
- Dual-bank Flash for safe in-application programming （对比 ATSAM3U2EA-AU)
- Same die in tape-and-reel packaging code （对比 ATSAM3U4EA-AUR)
- Industrial temperature-grade pin-compatible variant （对比 ATSAM3U4EA-CU)
设计说明
Place a 100 nF ceramic decoupling capacitor as close as possible to every VDDIO and VDDCORE pin, and add a bulk 4.7 uF to 10 uF tantalum or ceramic on the main 3.3V rail. The SAM3U's internal voltage regulator (VDDOUT) requires its own 1 uF + 100 nF pair; insufficient decoupling causes VDDOUT ripple and code-fetch failures at 96 MHz. Brown-out detection (BOD) is enabled by default at 1.62V - leave it on unless an external supervisor overrides it.
Use a continuous ground plane beneath the LQFP-144 footprint and route USB DP/DM as a 90 ohm differential pair of matched length to the connector, keeping the pair over unbroken ground. Place the 12 MHz crystal within 5 mm of XIN/XOUT with short, symmetric traces and a guard ring tied to ground. Avoid routing high-speed signals (SPI, USB) under the crystal or across plane splits; this prevents reference spurs and EMI re-radiation.
Do not assume Flash executes in zero wait-state from cold boot - the flash accelerator remapping sequence must be enabled in software after reset, otherwise code runs at reduced speed. Watch-dog timer is enabled by default and locks the JTAG interface after a timeout in some configurations - clear the WDT and unlock the JTAG lock-bit during early firmware bring-up. Also note that the 144-pin variant has five VDDIO domains; tying all to 3.3V is acceptable but partial power-down of unused domains saves quiescent current.
合规信息
RoHS and lead-free per Microchip product page. AEC-Q100 not applicable (industrial MCU, not automotive qualified). REACH compliance per Microchip declaration.
