CDK8307AILP64 - 12/13-bit Octal Ultra-Low Power LVDS ADC | MaxLinear
料号： CDK8307AILP64 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.65 | $256.50 |
| 100 | $22.8 | $2,280.00 |
| 500 | $20.52 | $10,260.00 |
| 1,000 | $18.45 | $18,450.00 |
CDK8307AILP64 概述
A pipelined ADC is a high-speed converter architecture that uses multiple low-resolution stages to digitize an analog signal, trading slightly higher latency than successive-approximation converters for dramatically higher sample rates and multi-channel integration. The CDK8307 family positions itself within the analog-to-digital converter hierarchy as a multi-channel data-acquisition building block used in the broader mixed-signal and data-converter IC family. Each LVDS (Low-Voltage Differential Signaling) output serializes the conversion result onto a small number of differential pairs, simplifying board routing and enabling direct FPGA connectivity.
Key specifications include 12/13-bit selectable resolution, sample rates of 20/40/50/65/80 MSPS, eight simultaneously-sampling channels, internal reference circuitry, and per-channel plus global power-down modes for energy-aware system design. The device is designed to interface directly with FPGAs from leading vendors, with LVDS serial output streams aligned for easy capture in the FPGA's high-speed transceiver or LVDS buffer logic. The proprietary architecture achieves low power per channel while maintaining AC performance across the supported sample-rate range.
Typical applications include medical imaging systems, multi-channel communications infrastructure, portable and battery-powered test equipment, industrial data acquisition modules, and any multi-sensor array requiring synchronized eight-channel sampling. Per-channel shutdown allows unused channels to be turned off, reducing the average power consumption of a partially populated system significantly compared with always-on designs.
Designers should plan decoupling close to each supply pin and follow the LVDS output routing guidelines in the manufacturer datasheet to maintain signal integrity across the eight serial lanes. The serial programming interface allows per-channel resolution selection, sample-rate configuration, and shutdown control, enabling software-defined power management. No mid-band analog trim is required thanks to the integrated internal reference.
直接替换替代料： CDK8307AILP64 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CDK8307AILP64 （相同外形与封装尺寸） ——差异在于 Control Interface, Package, Reference, Resolution, Architecture.
快速对比工具——选择替代料号进行并排对比：
CDK8307CILP64
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$11.95 / 个
查看数据手册 →CDK8307AILP64G
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
CDK8307BILP64
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$21.4 / 个
查看数据手册 →ADS5281IRGCT
✅ 直接替换📋 参考替代料（不在目录中）
ADS5282IRGCT
✅ 直接替换📋 参考替代料（不在目录中）
CDK8307AILP64 最大额定值与电气特性
| 分辨率 | 12/13-bit (selectable) |
| Number of Channels | 8 (simultaneous sampling) |
| Sample Rate Range | 20 / 40 / 50 / 65 / 80 MSPS |
| Architecture | Pipelined ADC with proprietary core |
| Output Interface | Serial LVDS |
| Reference | Internal reference (integrated) |
| Power Dissipation (Typ) | Ultra-low power (per-channel shutdown) |
| Shutdown Modes | Per-channel + full-chip idle (via external pin) |
| Control Interface | Serial programming interface (SPI-style) |
| FPGA Compatibility | Designed to interface with major FPGA vendors |
| 封装 | 64-pin QFN (ILP64) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| Original Brand | Cadeka / Exar (now MaxLinear) |
CDK8307AILP64 引脚配置
| 引脚 1 | VD_A — Analog supply (channel) |
| 引脚 2 | GND_A — Analog ground |
| 引脚 3 | AINP1 — Channel 1 positive analog input |
| 引脚 4 | AINN1 — Channel 1 negative analog input |
| 引脚 5 | VCMA — Common-mode voltage |
| 引脚 6 | AINP2 — Channel 2 positive analog input |
| 引脚 7 | AINN2 — Channel 2 negative analog input |
| 引脚 8 | GND_A — Analog ground |
| 引脚 9 | AINP3 — Channel 3 positive analog input |
| 引脚 10 | AINN3 — Channel 3 negative analog input |
| 引脚 11 | AINP4 — Channel 4 positive analog input |
| 引脚 12 | AINN4 — Channel 4 negative analog input |
| 引脚 13 | VCMA — Common-mode voltage |
| 引脚 14 | GND_A — Analog ground |
| 引脚 15 | AINP5 — Channel 5 positive analog input |
| 引脚 16 | AINN5 — Channel 5 negative analog input |
| 引脚 17 | AINP6 — Channel 6 positive analog input |
| 引脚 18 | AINN6 — Channel 6 negative analog input |
| 引脚 19 | GND_A — Analog ground |
| 引脚 20 | AINP7 — Channel 7 positive analog input |
| 引脚 21 | AINN7 — Channel 7 negative analog input |
| 引脚 22 | AINP8 — Channel 8 positive analog input |
| 引脚 23 | AINN8 — Channel 8 negative analog input |
| 引脚 24 | VCMA — Common-mode voltage |
| 引脚 25 | VD_A — Analog supply |
| 引脚 26 | GND_D — Digital ground |
| 引脚 27 | VD_D — Digital supply |
| 引脚 28 | GND_D — Digital ground |
| 引脚 29 | CLK+ — Differential clock input (positive) |
| 引脚 30 | CLK- — Differential clock input (negative) |
| 引脚 31 | GND_D — Digital ground |
| 引脚 32 | IDLE — Full-chip idle control pin (function per register) |
| 引脚 33 | RESET — Hardware reset |
| 引脚 34 | CSB — Serial interface chip select (active low) |
| 引脚 35 | SCLK — Serial interface clock |
| 引脚 36 | SDIO — Serial interface data input/output |
| 引脚 37 | SDO — Serial interface data output |
| 引脚 38 | VD_D — Digital supply |
| 引脚 39 | GND_D — Digital ground |
| 引脚 40 | OUT1+ — LVDS serialized data output pair 1 positive |
| 引脚 41 | OUT1- — LVDS serialized data output pair 1 negative |
| 引脚 42 | OUT2+ — LVDS serialized data output pair 2 positive |
| 引脚 43 | OUT2- — LVDS serialized data output pair 2 negative |
| 引脚 44 | GND_D — Digital ground |
| 引脚 45 | OUT3+ — LVDS serialized data output pair 3 positive |
| 引脚 46 | OUT3- — LVDS serialized data output pair 3 negative |
| 引脚 47 | OUT4+ — LVDS serialized data output pair 4 positive |
| 引脚 48 | OUT4- — LVDS serialized data output pair 4 negative |
| 引脚 49 | DCLK+ — LVDS data clock positive |
| 引脚 50 | DCLK- — LVDS data clock negative |
| 引脚 51 | GND_D — Digital ground |
| 引脚 52 | OUT5+ — LVDS serialized data output pair 5 positive |
| 引脚 53 | OUT5- — LVDS serialized data output pair 5 negative |
| 引脚 54 | OUT6+ — LVDS serialized data output pair 6 positive |
| 引脚 55 | OUT6- — LVDS serialized data output pair 6 negative |
| 引脚 56 | OUT7+ — LVDS serialized data output pair 7 positive |
| 引脚 57 | OUT7- — LVDS serialized data output pair 7 negative |
| 引脚 58 | GND_D — Digital ground |
| 引脚 59 | OUT8+ — LVDS serialized data output pair 8 positive |
| 引脚 60 | OUT8- — LVDS serialized data output pair 8 negative |
| 引脚 61 | VD_D — Digital supply |
| 引脚 62 | GND_D — Digital ground |
| 引脚 63 | REFIO — Reference input/output (external reference bypass) |
| 引脚 64 | EP — Exposed pad / thermal pad (must be soldered to PCB ground for thermal dissipation) |
典型应用
CDK8307AILP64 适用于 7 应用s: Multi-Channel Data Acquisition Module, Medical Imaging Front-End, Wireless Communications Baseband, Portable / Battery-Powered Test Equipment, Industrial Automation & Multi-Sensor Arrays, Radar / Phased-Array Signal Processing, Audio / Acoustic Measurement Arrays.
Multi-Channel Data Acquisition Module
The CDK8307AILP64's 8 simultaneous-sampling channels at up to 80 MSPS make it ideal for industrial data-acquisition modules where multiple sensor streams must be digitized with deterministic channel-to-channel phase alignment. According to the MaxLinear datasheet, the integrated internal reference and serial LVDS output simplify signal-chain design, while per-channel shutdown cuts power when only a subset of inputs is active, supporting partial-load efficiency. With a 12/13-bit selectable resolution, the device delivers sufficient dynamic range for vibration, acoustic, and vibration-monitoring arrays in factory automation.
推荐
Medical Imaging Front-End
Medical ultrasound and portable imaging front-ends benefit from the CDK8307AILP64's 8-channel parallel digitization up to 80 MSPS with serial LVDS output directly into an FPGA beamformer or image-processing pipeline. The MaxLinear datasheet highlights per-channel shutdown for energy-aware operation in battery-powered bedside units and the proprietary low-power architecture that keeps thermal dissipation manageable in compact enclosures. Selectable 12/13-bit resolution allows designers to tune SNR vs sample rate per transducer bandwidth, while the internal reference reduces external analog BOM.
推荐
Wireless Communications Baseband
Wireless baseband receivers and multi-antenna signal-processing cards use the CDK8307AILP64 to digitize 8 analog IF/RF channels simultaneously, with LVDS serialization keeping the FPGA-side pin count manageable. According to the MaxLinear datasheet, the proprietary pipelined core maintains SFDR performance across the 20-80 MSPS range, and the global idle pin enables fast standby transitions for TDMA/TDD systems. Per-channel shutdown is particularly useful in MIMO subsystems where individual antenna paths can be powered down during low-traffic intervals.
推荐
Portable / Battery-Powered Test Equipment
Handheld oscilloscope probes, portable logic analyzers, and field-test instruments benefit from the CDK8307AILP64's ultra-low-power architecture with per-channel shutdown, enabling 8-channel acquisition in battery-operated form factors. According to the MaxLinear datasheet, only active channels need to be powered, extending battery life for intermittent multi-channel captures, and the LVDS output streams minimize FPGA-side pin usage. The internal reference eliminates the need for a precision external reference IC, reducing BOM and board area in compact test gear.
推荐
Industrial Automation & Multi-Sensor Arrays
Factory-automation controllers and multi-sensor condition-monitoring systems use the CDK8307AILP64 to digitize 8 channels of vibration, current, or strain-gauge data simultaneously for FFT-based diagnostics. With selectable 12/13-bit resolution at up to 80 MSPS, the ADC captures rotating-machine signatures for predictive maintenance, while per-channel shutdown lets the system idle unused channels in a sparsely populated rack. The MaxLinear datasheet specifies that the serial LVDS output integrates cleanly with FPGA-based controllers and supports deterministic channel-to-channel sampling skew.
推荐
Radar / Phased-Array Signal Processing
Phased-array and AESA radar subsystems benefit from the CDK8307AILP64's 8-channel simultaneous sampling and deterministic latency, which preserves the inter-element phase relationships required for beamforming and angle-of-arrival estimation. According to the MaxLinear datasheet, the serial LVDS output format transports synchronized channel data over a small connector footprint, simplifying PCB routing between the analog front end and the FPGA beamformer. The proprietary low-power core improves array thermal budget, enabling higher-channel-count systems within the same cooling envelope.
推荐
Audio / Acoustic Measurement Arrays
Multi-microphone acoustic measurement arrays, beamforming microphone arrays, and acoustic-camera front-ends use the CDK8307AILP64 to digitize 8 microphone channels at up to 80 MSPS while preserving inter-channel phase coherence needed for direction-of-arrival algorithms. According to the MaxLinear datasheet, the integrated internal reference simplifies the analog front end, and per-channel shutdown minimizes power in beam patterns where only a subset of microphones are active. The compact 64-pin QFN package fits dense microphone-array PCB layouts.
推荐
推荐产品汇总
工程参考数据： CDK8307AILP64 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CDK8307CILP64 | CDK8307AILP64G | CDK8307BILP64 | ADS5281IRGCT | ADS5282IRGCT |
|---|---|---|---|---|---|---|
| Package | 64-pin QFN (ILP64) | 64-pin QFN (ILP64) - same family | 64-pin QFN (ILP64) - same die | 64-pin QFN (ILP64) - same family | 64-pin QFN (RGC) - same pin count | 64-pin QFN (RGC) - same pin count |
| Brand | MaxLinear | MaxLinear (same brand) | MaxLinear (same brand) | MaxLinear (same brand) | Texas Instruments | Texas Instruments |
| Resolution | 12/13-bit selectable | 12/13-bit selectable | 12/13-bit selectable | 12/13-bit selectable | 12-bit | 12-bit |
| Maximum Sample Rate | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS | 50 MSPS (-37%) | 65 MSPS (-19%) |
| Number of Channels | 8 | 8 | 8 | 8 | 8 | 8 |
| Output Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Parallel LVDS / DDR | Parallel LVDS / DDR |
| Internal Reference | Yes | Yes | Yes | Yes | External / internal select | External / internal select |
| Per-Channel Shutdown | Yes | Yes | Yes | Yes | Yes | Yes |
关键差异点
- Selectable 12/13-bit resolution per part number family （对比 ADS5281IRGCT)
- Up to 80 MSPS maximum sample rate versus 65 MSPS for closest TI octal ADC （对比 ADS5282IRGCT)
- Full-chip idle pin configurable via serial programming （对比 ADS5281IRGCT)
设计说明
The 64-pin QFN package has an exposed thermal pad on the underside that MUST be soldered to a ground copper pour on the top PCB layer for thermal dissipation, per the MaxLinear datasheet layout guidelines. Use thermal vias in a grid pattern (8-12 vias, 0.3 mm drill, 0.65 mm pitch) directly under the EP to carry heat into inner ground planes. Ground plane continuity between top and inner layers reduces both thermal resistance and electrical ground impedance at the high-edge rates of the LVDS outputs.
Estimated: at 80 MSPS across all 8 channels with LVDS outputs toggling at the data rate, route each LVDS pair as a tightly-coupled 100-ohm differential transmission line (trace width matched to 0.1 mm differential pair spacing) and minimize the distance to the FPGA receiving pins. Place the 0.1 uF supply decoupling capacitors within 2 mm of each VD_D pin, and add a 10 uF bulk capacitor nearby. Per the MaxLinear datasheet, the analog input traces should be length-matched within the channel group to preserve inter-channel sample skew below 50 ps.
Do not apply a clock signal to the CLK+/CLK- inputs before the supplies have ramped, as the proprietary pipelined core can latch up under partial bias; the MaxLinear datasheet specifies a power-sequencing requirement. Also, when using per-channel shutdown, ensure the LVDS biasing network reference is stable to avoid data-corrupt transitions on re-enabled channels. Verify the IDLE pin's configured function (set via serial programming) before relying on it for full-chip standby in production firmware.
合规信息
RoHS-compliant per MaxLinear product page. Original manufacturer Cadeka acquired by Exar (now MaxLinear). Automotive (AEC-Q100) qualification not applicable to this industrial/consumer ADC.
