DS90C383AMTD - 3.3V LVDS Transceiver | Texas Instruments
料号： DS90C383AMTD ✗ 停产DS90C383AMTD 概述
An LVDS transceiver is an interface IC that converts parallel CMOS/TTL data into low-voltage differential signals for transmission between circuit boards or display modules. FPD-Link combines parallel data and clock transmission over differential pairs, while LVDS provides low-voltage signaling, common-mode rejection, and reduced EMI sensitivity compared with single-ended interconnects. Within the signal-chain hierarchy, this device is an FPD-Link serializer/deserializer, an LVDS interface transceiver, and a semiconductor-level display connectivity solution.
The DS90C383AMTD operates from a 3 V to 3.6 V supply and supports programmable LVDS output described in the manufacturer datasheet. Its nominal 65 MHz FPD-Link clock supports transfer of a 24-bit display data stream, while the transmitter and receiver architecture allows the device to support both serialization and deserialization functions. The 56-TSSOP package provides a conventional surface-mount interface for display-controller and flat-panel systems.
Its architecture is centered on parallel CMOS/TTL signaling at the host interface and differential LVDS signaling across the panel link. Backward compatibility with existing 5 V FPD-Link systems is discussed in the manufacturer datasheet, providing an upgrade path toward 3.3 V equipment. The exact programmable output behavior, clocking requirements, and system timing should be implemented from the timing diagrams and pin descriptions in that datasheet.
Typical applications include small-format LCD panel links, digital video interface connections, industrial flat-panel displays, and embedded display systems that connect a graphics controller or FPGA to a display. Using the FPD-Link architecture can reduce the number of single-ended traces crossing between boards while supporting a deterministic parallel-data and differential-link structure.
Designers should preserve the required differential pair geometry, provide suitable bypass capacitance, and observe the supply and ground requirements shown in the manufacturer datasheet. LVDS receiver and transmitter layout, connector transitions, and cable routing should be treated as an impedance-controlled interface rather than as ordinary low-speed digital routing.
This page combines the manufacturer interface description, available supply and package information, application guidance, and a conservative engineering assessment of replacement options. It also distinguishes true same-footprint alternatives from related interface ICs that require circuit changes, helping designers evaluate PCB reuse without confusing protocol similarity with pin compatibility.
直接替换替代料： DS90C383AMTD ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
DS90C383SLCX
✅ 直接替换📋 参考替代料（不在目录中）
DS90C383AMTD 规格参数
| Device Type | Programmable LVDS transmitter/receiver |
| Protocol | FPD-Link |
| Number of Drivers/Receivers | 1/1 |
| Supply Voltage Range | 3 V to 3.6 V |
| Nominal Supply Voltage | 3.3 V |
| Parallel Data Width | 24 bits |
| Link Clock Frequency | 65 MHz |
| Signaling | LVDS |
| 封装 | 56-pin TSSOP (0.240, 6.10 mm width) |
| Packaging | Tube |
| 安装类型 | Surface mount |
DS90C383AMTD 56-pin tssop (0.240, 6.10 mm width) 引脚配置指南
DS90C383AMTD（56-pin tssop (0.240, 6.10 mm width) 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： DS90C383AMTD.
请参阅 数据手册 以查看完整引脚配置。
典型应用
DS90C383AMTD 适用于 6 应用s: Small-Flat-Panel LCD Display Interface, Industrial Human-Machine Interface Display, Embedded LCD Controller Interface, Digital Video Panel Link, FPGA-Based Video Output, Medical Panel Connection.
Small-Flat-Panel LCD Display Interface
The DS90C383AMTD fits controller-to-panel links requiring a 24-bit parallel data path and differential FPD-Link signaling. Its 65 MHz nominal link clock and 3 V to 3.6 V supply support 3.3 V display-controller environments, while the one-transmitter/one-receiver arrangement supports bidirectional system roles. Place the device at the appropriate end of the FPD-Link connection and follow the manufacturer timing diagrams for clocking and data validation. Differential routing reduces the number of single-ended traces over the cable or board interface, but correct pair geometry and impedance continuity remain essential.
推荐
Industrial Human-Machine Interface Display
An industrial HMI can use the DS90C383AMTD to carry 24-bit display data from a graphics controller or embedded processor to a remote panel. The 65 MHz FPD-Link clock provides a defined high-speed display transport, and the 3.3 V operating range simplifies integration with modern digital display electronics. Use the manufacturer F384 timing information to establish the relationship between parallel data, transmitted clock, and receiver data. For industrial deployment, verify the exact temperature grade and isolation requirements, then protect the interface from cable transients and maintain controlled return paths.
推荐
Embedded LCD Controller Interface
The DS90C383AMTD is suitable for an embedded display subsystem that exposes a 24-bit parallel interface at the controller and uses LVDS differential signaling across a board-to-panel connection. Its 65 MHz link clock and one transmitter/one receiver organization allow the same interface family to participate in panel communication. Place bypass and interface components close to the device, then route each differential pair directly to the destination connector. Validate setup time, hold time, clock phase, and reset behavior using the manufacturer datasheet because those details govern reliable display updates.
推荐
Digital Video Panel Link
The DS90C383AMTD can form part of a digital video-panel link carrying a 24-bit pixel stream over FPD-Link rather than a collection of single-ended parallel outputs. The 65 MHz clock and LVDS outputs are intended for display-oriented point-to-point connections, including video timing generated by an FPGA or graphics engine. The principal engineering benefit is a structured differential interface with fewer signal conductors across the link. The PCB still requires matched pair geometry, controlled impedance, proper grounding, and connector transitions that preserve differential timing.
推荐
FPGA-Based Video Output
An FPGA video engine can connect to a flat-panel destination through the DS90C383AMTD when the required pixel width, clock rate, and FPD-Link timing align with the target panel. The device accepts a 24-bit parallel data stream and serializes it through the LVDS transmit function for the panel link. This arrangement allows the FPGA to retain pixel timing and synchronization while reducing board-level trace count. The interface design should include deliberate clock routing, I/O-standard compatibility checks, and FPGA timing constraints based on the manufacturer’s input and output timing tables.
推荐
Medical Panel Connection
A medical display subsystem can use the DS90C383AMTD for a deterministic 24-bit display link when the required panel timing is supported. Its nominal 65 MHz FPD-Link operation provides a defined transport rate, and the LVDS interface is appropriate for compact panel cables where differential routing offers a controlled signal path. Because the exact operating-temperature and reliability requirements are not stated on this product page, medical use requires review against the manufacturer datasheet and the applicable system safety requirements. Do not infer medical qualification from the interface function alone.
推荐
推荐产品汇总
工程参考数据： DS90C383AMTD ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DS90C383SLCX |
|---|---|---|
| Package | 56-TSSOP | 56-TSSOP |
| Brand | Texas Instruments | Texas Instruments |
关键差异点
- Integrated FPD-Link transmit and receive functions （对比 DS90C383SLCX)
- 24-bit parallel display-data path （对比 DS90C383SLCX)
- Single 3.3 V supply range （对比 DS90C383SLCX)
设计说明
Route every LVDS pair as a continuous differential pair with uniform spacing and geometry from the DS90C383AMTD through connectors or cables to the receiving endpoint. Avoid splitting a pair, changing reference-plane transitions abruptly, or routing it adjacent to high-current switching nodes. The 65 MHz FPD-Link clock should be considered when reviewing trace length, pair symmetry, and return-path continuity.
Place input, output, bypass, and interface-routing components close to the TSSOP pins according to the manufacturer datasheet. Keep the device ground connections short and provide a low-impedance return path for both CMOS and differential signals. Because the 56-pin package has no exposed pad listed on this product page, use the manufacturer connection diagram rather than assuming thermal-pad connections.
Do not substitute a generic LVDS transceiver solely because it has a comparable data rate. The target device implements a 24-bit, 65 MHz FPD-Link interface with one transmitter and one receiver, so a replacement must also match pin functions, supply levels, clock relationships, timing margins, and enable or reset behavior. Related SN75LVDS83ADGG and SN65LVDS93ADGG devices require circuit review and are not confirmed drop-ins.
合规信息
No explicit compliance declarations were identified for this exact MPN. The manufacturer datasheet should be reviewed for orderable lead-free finish information and environmental declarations before production release.
