DS90LV032ATM - 400 Mbps 4-Channel LVDS Receiver | Texas Instruments
料号： DS90LV032ATM ✓ 量产中DS90LV032ATM 概述
An LVDS receiver is an interface circuit that recovers a digital signal from a small differential voltage carried over a balanced pair of conductors. LVDS belongs to the broader class of differential line receivers and interface ICs used to move high-speed data reliably between boards, backplanes, and rack-mounted systems. The DS90LV032A accepts low-voltage differential signals, typically 350 mV, and translates them into CMOS-compatible logic levels for downstream digital circuits.
Key features of the DS90LV032ATM include four independent receiver channels, data-rate operation above 400 Mbps, and a single 3 V supply. The receiver architecture is suited to low-power consumption and high-speed digital communication. The 16-pin SOIC package allows direct comparison with other 16-pin LVDS receiver families, although input and output pin functions should always be verified against the specific manufacturer datasheet before substitution.
The DS90LV032A is commonly used in point-to-point LVDS links, test and measurement equipment, industrial control systems, and digital backplanes. Its differential inputs help reject common-mode noise, while the CMOS outputs connect directly to FPGA, ASIC, or other digital logic inputs. The device supports data rates beyond 400 Mbps, making it appropriate for high-speed clock, control, and data-transfer connections.
Designers should pay attention to differential pair routing, controlled-impedance transmission lines, connector and via geometry, and the receiver supply decoupling. The TI DS90LV032A datasheet is the authoritative source for input thresholds, propagation delay, supply-current behavior, and absolute maximum ratings. The manufacturer product page identifies the DS90LV032A as an active 3 V LVDS quad CMOS differential line receiver, while the DS90LV032ATM orderable designation is listed in a 16-pin SOIC package.
This page combines the manufacturer datasheet, product-page information, distributor records, and cross-reference results for the DS90LV032ATM. It also provides application guidance, package-level design notes, comparison parameters, and drop-in alternative candidates for engineers evaluating an LVDS receiver redesign or second-source plan.
直接替换替代料： DS90LV032ATM ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
DS90LV032ATM/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
DS90LV032ATMX/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
DS90LV027ATMX/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
DS90LV017ATM
✅ 直接替换联系询价
查看数据手册 →AM26LV32EIDR
✅ 直接替换📋 参考替代料（不在目录中）
DS90LV032ATM 规格参数
| Device Type | LVDS quad differential line receiver |
| Number of Receivers | 4 channels |
| Number of Drivers | 0 drivers |
| 电源电压 | 3 V to 3.6 V |
| Nominal Supply Voltage | 3 V |
| Maximum Data Rate | Greater than 400 Mbps |
| Equivalent Clock Rate | 200 MHz |
| Input Differential Voltage | 350 mV typical |
| Output Logic Level | 3 V CMOS |
| Technology | Low Voltage Differential Signaling (LVDS) |
| 封装 | 16-pin narrow SOIC (D) |
| Package Type | SOIC narrow |
| 安装类型 | Surface Mount |
| 工作温度 | -40°C to 85°C |
| 生命周期状态 | Active |
DS90LV032ATM 引脚配置
| 引脚 1 | 1A+ — Non-inverting differential input for receiver 1 |
| 引脚 2 | 1A- — Inverting differential input for receiver 1 |
| 引脚 3 | 1Y — CMOS output for receiver 1 |
| 引脚 4 | GND — Ground |
| 引脚 5 | 2Y — CMOS output for receiver 2 |
| 引脚 6 | 2A- — Inverting differential input for receiver 2 |
| 引脚 7 | 2A+ — Non-inverting differential input for receiver 2 |
| 引脚 8 | VCC — Positive supply connection |
| 引脚 9 | 3A+ — Non-inverting differential input for receiver 3 |
| 引脚 10 | 3A- — Inverting differential input for receiver 3 |
| 引脚 11 | 3Y — CMOS output for receiver 3 |
| 引脚 12 | GND — Ground |
| 引脚 13 | 4Y — CMOS output for receiver 4 |
| 引脚 14 | 4A- — Inverting differential input for receiver 4 |
| 引脚 15 | 4A+ — Non-inverting differential input for receiver 4 |
| 引脚 16 | VCC — Positive supply connection |
典型应用
DS90LV032ATM 适用于 6 应用s: FPGA Board-to-Board LVDS Link, Industrial Control Backplane, Digital Test and Measurement Equipment, Processor and ASIC Interconnect, Clock Distribution over LVDS, Low-Power LVDS Interface Consolidation.
FPGA Board-to-Board LVDS Link
The DS90LV032ATM fits four high-speed LVDS inputs received from a transmitting FPGA, ASIC, or clock generator. Its greater-than-400-Mbps capability corresponds to a 200 MHz clock rate, while the 350 mV typical differential input supports the standard low-voltage LVDS interface. Place the receiver close to the connector or board edge, route each input as a coupled differential pair, and provide a local 3 V supply with high-frequency decoupling. The CMOS outputs then feed the destination FPGA or digital controller.
推荐
Industrial Control Backplane
A multi-lane control backplane can use the DS90LV032ATM to recover four low-voltage differential signals carrying synchronized commands or status data. The receiver supports rates above 400 Mbps and translates each pair into a 3 V CMOS logic level for industrial controllers. Controlled-impedance routing and a continuous ground plane are important at industrial temperatures and across connector transitions. The -40°C to 85°C operating range supports industrial equipment, subject to final qualification of the complete assembly.
推荐
Digital Test and Measurement Equipment
The DS90LV032ATM is appropriate for test instruments that receive high-speed differential commands, triggers, or data from remote modules. Four receiver channels provide compact multi-lane connectivity without requiring four separate single-channel packages. Its low-voltage differential inputs help reject common-mode noise generated by switching test circuitry, while the CMOS outputs can connect to FPGA-based acquisition logic. Validate eye margin, jitter, and channel-to-channel timing across the complete cable and connector path.
推荐
Processor and ASIC Interconnect
The DS90LV032ATM can terminate four LVDS inputs from a processor, ASIC, or peripheral and present standard CMOS outputs to internal logic. Its 3 V supply operation and four-channel integration simplify point-to-point board links, while data rates above 400 Mbps provide headroom for transfer clocks and parallel data lanes. Keep the receiver supply quiet and decoupled near the package, and confirm the source-device output levels, rise and fall times, and LVDS compliance before layout release.
推荐
Clock Distribution over LVDS
The DS90LV032ATM can receive a 200 MHz differential clock and three additional differential channels, making it suitable for multi-drop clock-and-data distribution where the physical topology supports LVDS. Supporting rates above 400 Mbps provide margin for the 200 MHz operating point identified for the family. Place the receiver at the far end of the controlled-impedance link, observe the source termination and connector requirements in the TI application information, and verify acquisition margin on the target instrument.
推荐
Low-Power LVDS Interface Consolidation
Consolidating four LVDS inputs into one 16-pin SOIC reduces the component and routing burden compared with four separate single-channel receivers. The DS90LV032ATM provides a 3 V CMOS interface and operation above 400 Mbps while retaining the compact package used in many communication boards. Because receiver input thresholds and timing can differ between similar families, review the specific alternative datasheet whenever this consolidation is used as a second-source or cost-reduction measure.
推荐
推荐产品汇总
工程参考数据： DS90LV032ATM ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DS90LV032ATM/NOPB | DS90LV032ATMX/NOPB | DS90LV027ATMX/NOPB | DS90LV017ATM | AM26LV32EIDR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 16-pin narrow SOIC (D) | 16-pin narrow SOIC (D) | 16-pin narrow SOIC (D) | 16-pin narrow SOIC (D) | 16-pin narrow SOIC (D) | 16-pin narrow SOIC (D) |
| Device Function | Quad LVDS differential line receiver | Quad LVDS differential line receiver | Quad LVDS differential line receiver | LVDS receiver family candidate | LVDS receiver family candidate | Differential line receiver candidate |
关键差异点
- Four LVDS inputs consolidated in one compact receiver （对比 DS90LV017ATM)
- High-rate operation for clock and data links （对比 DS90LV027ATMX/NOPB)
- Direct 3 V CMOS output interface （对比 AM26LV32EIDR)
- Compact 16-pin narrow SOIC implementation （对比 DS90LV032ATMX/NOPB)
设计说明
Route each LVDS input as a closely coupled differential pair over a continuous reference plane. Keep the two conductors in one layer where practical, maintain consistent spacing, avoid stubs, and minimize vias. The receiver should be placed near the connector or link endpoint so that connector and test-point discontinuities do not create excessive reflection on the high-speed channel.
Provide a low-impedance 3 V supply with local high-frequency decoupling close to the device supply pins. The DS90LV032A operates from 3 V to 3.6 V, and noisy supply distribution can degrade output transitions or margin on sensitive links. Keep switching regulators and inductors away from the LVDS pair, and verify supply integrity at the receiver under worst-case data activity.
Do not assume that a receiver with a similar description has an interchangeable pinout. Before selecting DS90LV027ATMX/NOPB, DS90LV017ATM, or AM26LV32EIDR, compare differential-input polarity, output-pin positions, supply pins, input thresholds, propagation delay, and power-off behavior in each manufacturer datasheet. Also verify whether the source device expects the receiver's typical 350 mV differential input.
Validate the complete receiver-to-source path rather than only the IC-to-IC connection. Account for source rise and fall times, channel skew, connector loss, clock jitter, and the receiver's timing characteristics. The family supports rates in excess of 400 Mbps, but achieving reliable operation at 200 MHz requires a controlled-impedance channel and verified source-device compliance with LVDS.
合规信息
The manufacturer lists the DS90LV032A family as active. RoHS, REACH, halogen-free, and conflict-minerals status are not explicitly stated in the available records, so those fields remain unknown. Automotive qualification is not established for this orderable designation.
