DSPIC33FJ128MC708T-I/PT - 16-Bit 40MIPS 128KB Flash DSC | Microchip
料号： DSPIC33FJ128MC708T-I/PT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $9.1 | $91.00 |
| 100 | $8.2 | $820.00 |
| 500 | $7.45 | $3,725.00 |
| 1,000 | $6.75 | $6,750.00 |
DSPIC33FJ128MC708T-I/PT 概述
A Digital Signal Controller (DSC) is a hybrid MCU/DSP architecture that retains the deterministic interrupt response and peripheral set of a microcontroller while adding a hardware multiply-accumulate (MAC) engine and DSP-oriented instruction set. Within Microchip's portfolio, the dsPIC33F sits above PIC16/PIC18 general-purpose MCUs and below PIC32 MIPS-based microcontrollers, and is part of the broader power management / motor-control hierarchy that includes gate drivers, MOSFETs, and position sensors.
Key features include 16 KB SRAM, an 8-channel hardware Motor Control PWM (Motor PWM) module with complementary outputs and programmable dead time, a 16-channel 10-bit ADC with 4 sample-and-hold units, two UART, two SPI, one I2C, one CAN, and a 16-bit timer/counter. The I-grade industrial temperature range of -40C to +85C, 3.0 V to 3.6 V single-supply operation, and ICSP/in-circuit debug support make it suitable for harsh embedded environments.
Architecturally, the dsPIC33F core uses a modified Harvard architecture with a 16-bit data path and 24-bit instruction words, enabling single-cycle 16x16 MAC operations. The integrated DSP engine accelerates transforms, PID loops, and field-oriented control (FOC) algorithms at 40 MIPS, which is sufficient for sub-microsecond current-loop updates in BLDC/PMSM drives.
Typical applications include sensorless and sensored BLDC motor drives, PMSM field-oriented control, industrial inverters, ACIM variable-frequency drives, and digital power conversion. Pairing the DSC with a gate driver such as the MCP8025 or three-phase MOSFET bridges (e.g., NCPFamily 600V parts) builds a complete motor-control node.
When designing with this part, allocate PCB area for the 12x12 mm TQFP and route the analog VDD/VSS pair separately from the digital supply to preserve ADC accuracy. Plan the PWM-ADC synchronization carefully: the ADC must sample within the PWM cycle to avoid aliasing of current-sense signals.
This page synthesizes distributor pricing, drop-in dsPIC33F alternatives, and practical motor-control design notes not consolidated in the manufacturer datasheet.
直接替换替代料： DSPIC33FJ128MC708T-I/PT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： DSPIC33FJ128MC708T-I/PT （相同外形与封装尺寸） ——差异在于 Operating Temperature, Package, ADC, CPU Speed, Core Architecture.
快速对比工具——选择替代料号进行并排对比：
DSPIC33FJ128MC708A-I/PT
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
DSPIC33FJ128MC708AT-I/PT
✅ 直接替换✓ 有现货
$4.8 / 个
查看数据手册 →DSPIC33FJ128MC706AT-I/PT
✅ 直接替换✓ 有现货
$8.15 / 个
查看数据手册 →DSPIC33FJ128MC706A-I/PT
✅ 直接替换✓ 有现货
$5.2 / 个
查看数据手册 →DSPIC33FJ128MC510A-I/PT
✅ 直接替换📋 参考替代料（不在目录中）
DSPIC33FJ128GP710AT-I/PT
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$6.05 / 个
查看数据手册 →DSPIC33FJ128MC708T-I/PT 最大额定值与电气特性
| Core | dsPIC33F (16-bit DSC) |
| CPU Speed | 40 MIPS |
| Program Memory (Flash) | 128 KB (128K x 8) |
| RAM | 16 KB |
| 电源电压 | 3.0 V to 3.6 V |
| 工作温度 | -40C to +85C (Industrial) |
| I/O Pins | 21 (general-purpose) |
| Motor Control PWM | 8 channels with complementary outputs and programmable dead time |
| ADC | 10-bit, up to 16 channels, 4 S&H |
| UART | 2 |
| SPI | 2 |
| I2C | 1 |
| CAN | 1 |
| Timers | 16-bit timer/counter modules |
| 封装 | 80-pin TQFP (PT), 12x12 mm |
| 安装类型 | Surface Mount |
| Debug Interface | ICSP / ICD |
| RoHS 状态 | Compliant |
DSPIC33FJ128MC708T-I/PT 引脚配置
| 引脚 1 | VSS — Digital ground |
| 引脚 2 | RP0/PWM1H — Remappable I/O / Motor PWM channel 1 high |
| 引脚 3 | RP1/PWM1L — Remappable I/O / Motor PWM channel 1 low |
| 引脚 4 | RP2/PWM2H — Remappable I/O / Motor PWM channel 2 high |
| 引脚 5 | RP3/PWM2L — Remappable I/O / Motor PWM channel 2 low |
| 引脚 6 | RP4/PWM3H — Remappable I/O / Motor PWM channel 3 high |
| 引脚 7 | RP5/PWM3L — Remappable I/O / Motor PWM channel 3 low |
| 引脚 8 | VSS — Digital ground |
| 引脚 9 | RP6/PWM4H — Remappable I/O / Motor PWM channel 4 high |
| 引脚 10 | RP7/PWM4L — Remappable I/O / Motor PWM channel 4 low |
| 引脚 11 | RP8 — Remappable I/O |
| 引脚 12 | RP9 — Remappable I/O |
| 引脚 13 | RP10 — Remappable I/O |
| 引脚 14 | RP11 — Remappable I/O |
| 引脚 15 | VSS — Digital ground |
| 引脚 16 | RP12 — Remappable I/O |
| 引脚 17 | RP13 — Remappable I/O |
| 引脚 18 | RP14 — Remappable I/O |
| 引脚 19 | RP15 — Remappable I/O |
| 引脚 20 | VDD — Digital supply 3.3V |
| 引脚 21 | MCLR — Master clear (reset, active low) |
| 引脚 22 | PGC — ICSP clock |
| 引脚 23 | PGD — ICSP data |
| 引脚 24 | VSS — Digital ground |
| 引脚 25 | OSC1 — Crystal oscillator input |
| 引脚 26 | OSC2 — Crystal oscillator output |
| 引脚 27 | AN0/VREF+ — Analog input 0 / ADC Vref+ |
| 引脚 28 | AN1/VREF- — Analog input 1 / ADC Vref- |
| 引脚 29 | AN2 — Analog input 2 |
| 引脚 30 | AN3 — Analog input 3 |
| 引脚 31 | AN4 — Analog input 4 |
| 引脚 32 | AN5 — Analog input 5 |
| 引脚 33 | AVDD — Analog supply 3.3V |
| 引脚 34 | AVSS — Analog ground |
| 引脚 35 | AN6 — Analog input 6 |
| 引脚 36 | AN7 — Analog input 7 |
| 引脚 37 | AN8 — Analog input 8 |
| 引脚 38 | AN9 — Analog input 9 |
| 引脚 39 | AN10 — Analog input 10 |
| 引脚 40 | AN11 — Analog input 11 |
| 引脚 41 | AN12 — Analog input 12 |
| 引脚 42 | AN13 — Analog input 13 |
| 引脚 43 | AN14 — Analog input 14 |
| 引脚 44 | AN15 — Analog input 15 |
| 引脚 45 | VDD — Digital supply 3.3V |
| 引脚 46 | VSS — Digital ground |
| 引脚 47 | U1RX/RP16 — UART1 RX / remappable I/O |
| 引脚 48 | U1TX/RP17 — UART1 TX / remappable I/O |
| 引脚 49 | U2RX/RP18 — UART2 RX / remappable I/O |
| 引脚 50 | U2TX/RP19 — UART2 TX / remappable I/O |
| 引脚 51 | SDO1/RP20 — SPI1 data out / remappable I/O |
| 引脚 52 | SDI1/RP21 — SPI1 data in / remappable I/O |
| 引脚 53 | SCK1/RP22 — SPI1 clock / remappable I/O |
| 引脚 54 | SS1/RP23 — SPI1 slave select / remappable I/O |
| 引脚 55 | SDO2/RP24 — SPI2 data out / remappable I/O |
| 引脚 56 | SDI2/RP25 — SPI2 data in / remappable I/O |
| 引脚 57 | SCK2/RP26 — SPI2 clock / remappable I/O |
| 引脚 58 | SS2/RP27 — SPI2 slave select / remappable I/O |
| 引脚 59 | SDA1/RP28 — I2C1 data / remappable I/O |
| 引脚 60 | SCL1/RP29 — I2C1 clock / remappable I/O |
| 引脚 61 | C1RX/RP30 — CAN1 RX / remappable I/O |
| 引脚 62 | C1TX/RP31 — CAN1 TX / remappable I/O |
| 引脚 63 | T1CK/RP32 — Timer1 clock / remappable I/O |
| 引脚 64 | T2CK/RP33 — Timer2 clock / remappable I/O |
| 引脚 65 | T3CK/RP34 — Timer3 clock / remappable I/O |
| 引脚 66 | T4CK/RP35 — Timer4 clock / remappable I/O |
| 引脚 67 | T5CK/RP36 — Timer5 clock / remappable I/O |
| 引脚 68 | IC1/RP37 — Input capture 1 / remappable I/O |
| 引脚 69 | IC2/RP38 — Input capture 2 / remappable I/O |
| 引脚 70 | OC1/RP39 — Output compare 1 / remappable I/O |
| 引脚 71 | OC2/RP40 — Output compare 2 / remappable I/O |
| 引脚 72 | VDD — Digital supply 3.3V |
| 引脚 73 | VSS — Digital ground |
| 引脚 74 | INT0/RP41 — External interrupt 0 / remappable I/O |
| 引脚 75 | INT1/RP42 — External interrupt 1 / remappable I/O |
| 引脚 76 | INT2/RP43 — External interrupt 2 / remappable I/O |
| 引脚 77 | RTCC/RP44 — Real-time clock alarm / remappable I/O |
| 引脚 78 | FLTA/RP45 — PWM fault input / remappable I/O |
| 引脚 79 | NC — Not connected (per datasheet) |
| 引脚 80 | NC — Not connected (per datasheet) |
典型应用
DSPIC33FJ128MC708T-I/PT 适用于 6 应用s: Brushless DC (BLDC) Motor Drive, Permanent Magnet Synchronous Motor (PMSM) Field-Oriented Control, AC Induction Motor Variable-Frequency Drive, Switched Reluctance Motor (SRM) Control, Digital Power Conversion (PFC + LLC), Industrial Servo and Robotics Motion Control.
Brushless DC (BLDC) Motor Drive
The DSPIC33FJ128MC708T-I/PT is a strong fit for BLDC motor drives because of its 8-channel Motor Control PWM with complementary outputs and programmable dead time, plus a 10-bit ADC with 4 sample-and-hold units that can sample all three phase currents simultaneously. At 40 MIPS, the DSC executes Park/Clarke transforms, PID current loops, and back-EMF observer routines inside a single PWM period (typically 50 us at 20 kHz switching), leaving headroom for housekeeping and communication tasks. The on-chip CAN and UART peripherals support automotive-style drive networks, while the industrial -40C to +85C operating range handles under-hood and industrial cabinet environments.
推荐
Permanent Magnet Synchronous Motor (PMSM) Field-Oriented Control
FOC algorithms on PMSMs require high-rate current-loop execution with synchronized ADC sampling, and the DSPIC33FJ128MC708T-I/PT delivers 40 MIPS plus dedicated Motor PWM with ADC-trigger alignment to make this tractable. The 16 KB of SRAM holds Park/Clarke state variables, observer buffers, and the speed/torque PI controllers without external memory. Designers pair this DSC with a digital resolver or Sin/Cos encoder for rotor position feedback; the device's QEI (Quadrature Encoder Interface) on timer inputs and CAN peripheral then close the position/speed loop into a host motion controller.
推荐
AC Induction Motor Variable-Frequency Drive
Three-phase AC induction motor (ACIM) VFDs rely on scalar V/Hz or indirect FOC, both of which run comfortably on the DSPIC33FJ128MC708T-I/PT at 40 MIPS. The Motor Control PWM supports space-vector modulation with dead-time insertion, while the 16-channel ADC reads DC-bus voltage, phase currents, and temperature feedback. The 128 KB Flash holds VFD state machines, slip-compensation tables, and protection routines (overcurrent, brownout, overtemperature). Industrial HVAC compressors and pump drives are the dominant deployment.
推荐
Switched Reluctance Motor (SRM) Control
Switched reluctance motors need precise commutation control on each phase and the DSPIC33FJ128MC708T-I/PT provides enough Motor PWM channels (8) and ADC triggers (4 S&H) to handle 4-phase or 6/8 SRM topologies. The 40 MIPS DSP engine runs instantaneous torque control and demagnetization energy-recovery routines, which require fast interrupt response times that the dsPIC33F architecture supports natively. SRM drives are common in high-reliability appliances, aerospace actuators, and traction applications.
推荐
Digital Power Conversion (PFC + LLC)
The DSPIC33FJ128MC708T-I/PT is widely used in digital power-conversion reference designs for interleaved PFC, LLC, and phase-shifted full-bridge converters. Its 40 MIPS execution enables average-current-mode control loops at 100 kHz switching, while the dedicated ADC with 4 S&H reads input voltage, input current, output voltage, and output current with predictable latency. The PWM module supports the leading-edge and trailing-edge modulation patterns required for interleaved topologies. Microchip's application notes AN1078 and AN1166 cover these topologies directly on this device family.
推荐
Industrial Servo and Robotics Motion Control
For multi-axis servo amplifiers and robotics motion-control nodes, the DSPIC33FJ128MC708T-I/PT handles one axis per device, executing the position/speed/current triple loop in firmware. The 16 KB RAM supports full state-feedback controllers, while the QEI peripheral interfaces directly with incremental encoders; the CAN peripheral backhauls motion data to a central controller. At -40C to +85C, the device suits factory-floor enclosures and robotic joint modules where reliability under thermal stress is essential.
推荐
推荐产品汇总
工程参考数据： DSPIC33FJ128MC708T-I/PT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DSPIC33FJ128MC708A-I/PT | DSPIC33FJ128MC708AT-I/PT | DSPIC33FJ128MC706AT-I/PT | DSPIC33FJ128MC706A-I/PT | DSPIC33FJ128MC510A-I/PT |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 80-pin TQFP (PT), 12x12 mm | 80-pin TQFP (PT), 12x12 mm | 80-pin TQFP (PT), 12x12 mm | 80-pin TQFP (PT), 12x12 mm | 80-pin TQFP (PT), 12x12 mm | 80-pin TQFP (PT), 12x12 mm |
| CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| Flash Memory | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| Supply Voltage | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V | 3.0 V to 3.6 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
关键差异点
- Dedicated 8-channel Motor Control PWM with hardware dead-time insertion （对比 DSPIC33FJ128GP710AT-I/PT)
- Industry-standard dsPIC33F instruction set with single-cycle MAC （对比 DSPIC33FJ128MC706AT-I/PT)
- Robust 4-sample-and-hold ADC for simultaneous phase-current sampling （对比 DSPIC33FJ128MC510A-I/PT)
设计说明
Estimated: at 80 MHz oscillator (40 MIPS) with all peripherals enabled, the DSPIC33FJ128MC708T-I/PT draws up to ~50 mA from a 3.3 V supply under full PWM load. Decouple VDD/AVDD with a 10 uF bulk cap and 0.1 uF + 1 nF ceramic caps placed within 5 mm of each pin pair; keep analog AVDD/AVSS star-routed separately from digital VDD to avoid injecting PWM switching noise into the ADC reference. Add a ferrite bead between VDD and AVDD if a shared regulator is used.
The 80-pin TQFP (12x12 mm) without an exposed pad dissipates roughly 1.5 W maximum. Estimated: at 3.3 V, 50 mA, and full peripheral activity, total package dissipation is about 165 mW, so the device is normally safe without a heatsink. Above ambient 60C in a sealed enclosure, place a 50x50 mm copper flood on the top layer connected to VSS to spread heat; the resulting theta_JA drop keeps junction rise below 30C.
Route the analog AN0-AN15 traces away from the PWM switching nets (PWM1H/L through PWM4H/L) to minimize capacitive coupling into ADC inputs. Place current-sense op-amp outputs within 25 mm of the ADC pins and use a 10 nF RC filter on each analog input if the source impedance exceeds 5 kohm. Keep the ICSP PGC/PGD pair short and well-clear of the high-current phase-switching paths.
Do not leave the MCLR pin floating; pull MCLR to VDD through a 10 kohm resistor with a 100 nF cap to VDD for noise immunity. The PGA (Program Gain Amplifier) and bandgap reference must be enabled before the ADC starts conversion - failure to wait the bandgap stabilization time (per datasheet AC characteristics) yields non-monotonic ADC results. Also confirm that the PWM fault pin (FLTA) is properly configured in firmware; an unexpected fault assertion will disable all PWM outputs.
Place the 80-pin TQFP on the top layer with a 4-layer stack-up using a continuous ground plane on layer 2 to provide a low-impedance return path for high-frequency switching. Route the oscillator traces (OSC1/OSC2) within 10 mm of the IC, guard them with a grounded copper pour, and keep them at least 5 mm away from PWM traces. Decouple each VDD/VSS pair with a 100 nF X7R 0402 ceramic cap directly on the power pins.
合规信息
RoHS and lead-free per Microchip product page. AEC-Q100 not applicable - this is an industrial-grade part (I suffix = -40C to +85C); for automotive AEC-Q100 qualified motor controllers see dsPIC33CK and dsPIC33CH families.