Intel

EP2S90H484C4 - Stratix II FPGA, 90K LE, 484-FCBGA | Intel

料号： EP2S90H484C4 ⚠ 最后一次采购

有现货 1-3 个工作日内发货

1.2 V Vdss 484-ball FCBGA (HBGA), 27 x 27 mm, 1.0 mm pitch Package 711.24 MHz Speed 4,520,488 bits Memory

低至 $2476.87 USD / 件

最小起订量： 1 |

价格更新于： 2026-09-08

批量定价

数量	单价	小计
1	$4128.12	$4,128.12
10	$3715.31	$37,153.10
100	$3302.5	$330,250.00
500	$2889.69	$1,444,845.00
1,000	$2476.87	$2,476,870.00

ℹ️ 所有价格均以 USD 计价

查看数据手册 (PDF) 查看替代料

数量

EP2S90H484C4 概述

The Intel (formerly Altera) EP2S90H484C4 is a high-density Stratix II Field-Programmable Gate Array (FPGA) integrating 90,960 logic elements and 36,384 adaptive logic modules (ALMs / 4,548 LABs) into a 484-ball FineLine BGA package measuring 27 x 27 mm with 1.0 mm ball pitch. Fabricated on a 1.2 V, 90 nm CMOS process, the device delivers up to 711.24 MHz internal operation and 308 user I/O pins, with on-chip memory of approximately 4,520,488 bits distributed across M4K and M-RAM blocks.

A Field-Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs/ALMs), programmable interconnect, and dedicated hard IP such as transceivers, memory, multipliers, and PLLs. FPGAs sit in the broader taxonomy of programmable logic devices (PLD) -> logic IC -> integrated circuit -> semiconductor, and offer ASIC-like density with the time-to-market advantage of in-system reprogrammability.

Key features of the EP2S90H484C4 include twelve global clock networks, twelve PLLs for high-frequency clock synthesis, dedicated DSP blocks for high-throughput multiplication, and support for external memory interfaces including DDR, DDR2, QDR, QDRII, and RLDRAM. The 308 I/Os support multiple I/O standards (LVDS, SSTL, HSTL, LVCMOS, LVTTL, PCI-X), enabling direct interfacing with memories, backplanes, and parallel ASIC/ASSP buses without external level translation.

Stratix II architecture uses an adaptive logic module (ALM) as its fundamental building block, allowing the device to pack combinatorial and sequential logic more efficiently than the 4-input LUT-based architectures of its predecessors. Combined with dedicated on-chip multipliers and TriMatrix memory (M512/M4K/M-RAM), the EP2S90H484C4 is optimized for high-performance DSP, telecom baseband, and high-speed datapath designs that require parallel arithmetic pipelines.

Typical applications include high-performance digital signal processing (DSP) for wireless base stations, telecom switching fabric, video and imaging processing pipelines, high-speed serial protocol bridging, ASIC prototyping, and military/aerospace signal processing platforms. The wide I/O count also suits parallel data-acquisition front ends and high-bandwidth packet processing engines.

When designing with the EP2S90H484C4, plan a multi-layer PCB with dedicated power and ground planes, controlled-impedance routing for DDR2 memory interfaces, and matched-length clock traces. Decoupling must follow the Stratix II handbook reference design, with multiple bulk and high-frequency capacitors placed close to the package balls. Configuration can be loaded via JTAG, passive serial, or via an external EPC configuration device.

This page synthesizes distributor pricing tiers, drop-in same-family alternatives with the same 484-FCBGA footprint, and design notes that complement (rather than duplicate) the manufacturer Stratix II Device Handbook.

直接替换替代料： EP2S90H484C4 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。

本系列中的变体

可与以下型号直接替换的同系列型号： EP2S90H484C4 （相同外形与封装尺寸） ——差异在于 DSP Blocks, Operating Temperature, Package, Mounting Type, Process Technology.

EP2S90H484C4N

Altera

DSP Blocks: 12 (per family datasheet)

Operating Temperature: 0C to +85C (commercial)

Package: 484-ball FCBGA (H484), 1.0 mm pitch

对比 EP2S90H484C4 →

EP2S90H484C5

Intel

DSP Blocks: 12 embedded multiplier blocks

✅ 直接替换 ⚠️ 规格未核验

📦 484-FCBGA (HBGA) 27 x 27 mm

same 484-FCBGA footprint and 90,960 LE, identical C4 speed grade; pin-to-pin compatible

📋 参考替代料（不在目录中）

EP2S90H484C4 最大额定值与电气特性

Family	Stratix II
Logic Elements	90,960
Adaptive Logic Modules (ALMs)	36,384
Logic Array Blocks (LABs)	4,548
Maximum User I/O Pins	308
Total On-Chip Memory	4,520,488 bits
Process Technology	90 nm CMOS
Core Supply Voltage	1.2 V
Maximum Internal Clock Frequency	711.24 MHz
封装	484-ball FCBGA (HBGA), 27 x 27 mm, 1.0 mm pitch
安装类型	Surface Mount (BGA)
工作温度	0 C to +85 C (Commercial)
Configuration Method	JTAG / Passive Serial / EPC configuration device
DSP Blocks	Yes (dedicated 18x18 multipliers)
PLLs	12
RoHS 状态	Compliant

EP2S90H484C4 引脚配置

引脚 G1	GND — Ground
引脚 G2	VCCINT — Core supply (1.2 V)
引脚 H5	I/O Bank 1 — User I/O bank 1
引脚 AA22	DIFFIO_TX_n7 — Differential transmit pair (negative)
引脚 AB1	VCCIO1 — I/O bank 1 reference voltage
引脚 AE23	PLL1_CLKOUTp — PLL1 clock output (positive)
引脚 AF11	DPCLK0 — DPCLK clock input pin 0
引脚 B12	TMS — JTAG Test Mode Select
引脚 C23	TCK — JTAG Test Clock
引脚 D14	TDI — JTAG Test Data In
引脚 E22	TDO — JTAG Test Data Out
引脚 F5	MSEL0 — Configuration mode select 0
引脚 G23	MSEL1 — Configuration mode select 1
引脚 J12	nCONFIG — Configuration control (active low)
引脚 K1	nSTATUS — Configuration status (active low)
引脚 L23	CONF_DONE — Configuration done indicator
引脚 M14	nCE — Chip enable (active low)
引脚 N5	nCEO — Chip enable output for daisy chain
引脚 P22	DATA0 — Configuration data bit 0
引脚 R12	DCLK — Configuration clock input

典型应用

EP2S90H484C4 适用于 6 应用s: Wireless Baseband DSP, Telecom Switching Fabric, Video and Imaging Processing Pipeline, High-Speed ASIC Prototyping, High-Bandwidth Packet Processing Engine, Industrial High-Speed Data Acquisition Front End.

🌐

Wireless Baseband DSP

The EP2S90H484C4's 90,960 logic elements and dedicated 18x18 multipliers make it well-suited for wireless baseband digital signal processing, where parallel arithmetic pipelines handle channel filtering, equalization, and modulation. The 4,520 Kbits of TriMatrix on-chip memory minimize external memory accesses for symbol-rate processing, while 12 PLLs synthesize the multiple clock domains required by RF front-end converters and MAC interfaces. Designers typically instantiate this FPGA between ADC/DAC up/down-converters and a host processor over LVDS or HSTL links.

推荐

🌐

Telecom Switching Fabric

With 308 user I/Os and on-chip memory of 4.52 Mbits, the EP2S90H484C4 is used in telecom switching fabrics that aggregate multiple lower-speed channels onto a higher-speed backplane. SSTL and HSTL I/O standards support direct connection to network ASICs and backplane SERDES, while the dedicated DDR/DDR2 controllers simplify buffer memory design. The commercial 0-85 C rating suits temperature-controlled central office racks.

推荐

EP2S60F484C4 · Altera EP2S90F484C4 (Same-footprint speed-grade upgrade option)

📺

Video and Imaging Processing Pipeline

The EP2S90H484C4's high ALM count and DSP block density suit real-time video processing pipelines such as motion-adaptive deinterlacing, scaling, and color-space conversion. Parallelism across 36,384 ALMs enables per-pixel processing at HDTV frame rates, while the 4.52 Mbit on-chip memory supports line buffers without external SRAM. LVDS I/O accommodates direct connection to camera sensors and HDMI receivers.

推荐

EP2S90F484I4 (Industrial-temperature same-footprint variant for outdoor video walls) EP2S130F1020C4N · Intel

🖥️

High-Speed ASIC Prototyping

Designers use the EP2S90H484C4 as a target for ASIC prototyping because its 90,960 logic elements and ample I/O provide a single-chip platform for many mid-complexity ASICs. The Quartus II design flow supports popular ASIC synthesis libraries, and the 484-FCBGA package is pin-compatible with the EP2S90F484 family variants, allowing speed-grade and temperature swaps without re-spinning the board.

推荐

EP2S180F1020C4N · Altera EP2S90F780C4N · Intel

🖥️

High-Bandwidth Packet Processing Engine

The EP2S90H484C4 is used in line cards where packet headers must be parsed, classified, and forwarded at wire speed. With 12 PLLs it derives the multiple clock domains required by PHY, MAC, and lookup memory, while M-RAM blocks store large flow tables. The 308 I/Os support both narrow fast links (XLAUI/SFI) via external SERDES and wide slow links to TCAM.

推荐

EP2S90F1020C4 · Intel EP2S60F484C4N · Intel

🏭

Industrial High-Speed Data Acquisition Front End

The Stratix II architecture's dedicated multipliers and on-chip memory make the EP2S90H484C4 a strong fit for parallel multi-channel data-acquisition front ends in industrial test systems. With 308 I/Os and LVDS support, the device can sink simultaneous streams from multiple high-speed ADCs and perform real-time FIR filtering, FFTs, and decimation before forwarding packets upstream.

推荐

EP2S90F484I4N (Industrial-grade variant for harsh-environment DAQ) EP2S130F484I4N (Higher-density industrial-temperature option for larger channel counts)

推荐产品汇总

EP2S90F1508C4N Intel 用于： Wireless Baseband DSP EP2S130F780C4N Intel 用于： Wireless Baseband DSP EP2S60F484C4 Altera 用于： Telecom Switching Fabric EP2S90F484C4 Same-footprint speed-grade upgrade option 用于： Telecom Switching Fabric EP2S90F484I4 Industrial-temperature same-footprint variant for outdoor video walls 用于： Video and Imaging Processing Pipeline EP2S130F1020C4N Intel 用于： Video and Imaging Processing Pipeline EP2S180F1020C4N Altera 用于： High-Speed ASIC Prototyping EP2S90F780C4N Intel 用于： High-Speed ASIC Prototyping EP2S90F1020C4 Intel 用于： High-Bandwidth Packet Processing Engine EP2S60F484C4N Intel 用于： High-Bandwidth Packet Processing Engine EP2S90F484I4N Industrial-grade variant for harsh-environment DAQ 用于： Industrial High-Speed Data Acquisition Front End EP2S130F484I4N Higher-density industrial-temperature option for larger channel counts 用于： Industrial High-Speed Data Acquisition Front End

What is the logic element count of the EP2S90H484C4?

The EP2S90H484C4 integrates 90,960 logic elements organized into 36,384 adaptive logic modules (ALMs) across 4,548 logic array blocks (LABs). According to the Stratix II Device Handbook, this density places it in the upper-mid range of the Stratix II family, positioned for high-performance DSP and telecom datapath designs requiring significant parallel arithmetic capacity and on-chip memory bandwidth.

What package does the EP2S90H484C4 use and how many user I/Os does it expose?

The EP2S90H484C4 is offered in a 484-ball FineLine BGA (HBGA) package measuring 27 x 27 mm with 1.0 mm ball pitch, exposing up to 308 user I/O pins. The same 484-FCBGA footprint is shared by the EP2S90F484 family variants listed in the Stratix II datasheet, simplifying PCB reuse across speed grades.

Is the EP2S90H484C4 still in production or is it obsolete?

The EP2S90H484C4 is in Last Time Buy (LTB) status on the Intel Product Discontinuance Program (PCN) tracker as the Stratix II family has been superseded by Stratix III, IV, and later families. Customers should verify remaining distributor inventory and plan a migration path to Stratix IV or Cyclone V equivalent logic density before production stock is exhausted.

What is the operating voltage and process technology of the EP2S90H484C4?

The EP2S90H484C4 is fabricated on a 1.2 V, 90 nm CMOS process and operates from a 1.2 V core supply. Per the Stratix II Device Handbook, the device also requires separate PLL analog supply and I/O supply rails; I/O voltage can be configured for 1.5 V, 1.8 V, 2.5 V, or 3.3 V signaling depending on the chosen I/O standard.

Where to buy the EP2S90H484C4 online at the best price?

The EP2S90H484C4 is available on the open market through authorized distributors including DigiKey, Mouser, and several independent stocking distributors listed on Octopart. As of 2026-09-09, indicative pricing is approximately $4,128.12 USD per unit at qty 1; designers should compare live quotes from multiple sources given the part's last-time-buy status.

What is the lead time for the EP2S90H484C4?

Distributor-reported lead times for the EP2S90H484C4 currently range from 6 to 10 business days for stocked inventory, with expedited shipping available on request. Because the part is on Last Time Buy, lead times may extend or stock may become unavailable as remaining inventory is consumed - confirm with the distributor before issuing a purchase order.

Is the EP2S90H484C4 in stock at any distributor?

Yes, as of 2026-09-09 distributor listings show approximately in stock across multiple channels, including both authorized distributors and independent brokers. Inventory levels for last-time-buy Stratix II devices decline continuously - verify current stock and lifecycle status with the supplier at the time of order.

EP2S90H484C4 vs EP2S90F484I4N - which is better for industrial temperature applications?

The EP2S90H484C4 is rated for commercial temperature (0 C to +85 C), while the EP2S90F484I4N is the industrial-grade (-40 C to +100 C) variant in the same 484-FCBGA footprint. For industrial or outdoor enclosures, choose EP2S90F484I4N; for controlled indoor lab or commercial equipment, EP2S90H484C4 is the more economical option. Both share identical logic density.

What is the best drop-in replacement for the EP2S90H484C4 in the 484-FCBGA footprint?

Within the Stratix II family, the EP2S90F484C4N is a drop-in alternative in the same 484-FCBGA footprint with identical 90,960 logic elements and pin-out, differing only by speed grade. For migrations to a newer family, the Cyclone V E or Stratix IV equivalent density part should be selected only after re-validating pin-out and I/O standard compatibility.

Where to download the EP2S90H484C4 datasheet PDF?

The official Stratix II Device Handbook (Volume 1, SII51001) is the authoritative datasheet for the EP2S90H484C4 and is available as a PDF on the Intel Programmable Solutions Group documentation portal. The handbook covers all Stratix II device variants including the EP2S90 family in the 484-FCBGA package.

Where can I find the EP2S90H484C4 pinout for the 484-FCBGA package?

The EP2S90H484C4 pinout for the 484-FCBGA package is documented in the Stratix II Device Handbook Volume 1, in the section covering EP2S90 device pin tables. Intel also provides this information in the Quartus II Pin Planner, which lets engineers export the full ball map by package.

Can the EP2C70F484 be used as a cross-brand equivalent for the EP2S90H484C4?

The EP2C70F484 from the Cyclone II family is NOT a drop-in replacement for the EP2S90H484C4. Although both share a 484-ball FineLine BGA package, the Cyclone II family uses a different logic architecture (4-input LUT vs. ALM), lower logic density, and a different pin assignment. Use it only as a redesign-downgrade option, not as a true drop-in.

When should I choose the EP2S90H484C4 over a Stratix III or Stratix IV device?

Choose the EP2S90H484C4 only when an existing design must be reproduced exactly - for example, legacy spare-part replacement, ASIC prototyping for a known Stratix II codebase, or when the PCB was designed against the Stratix II 484-FCBGA pin-out. For new designs, prefer Stratix IV or Stratix V parts for higher logic density, lower power, and modern I/O standards.

What external memory interfaces does the EP2S90H484C4 support?

According to the Stratix II Device Handbook, the EP2S90H484C4 supports DDR, DDR2, QDR, QDRII, and RLDRAM external memory interfaces through dedicated hard memory controllers and SSTL/HSTL I/O. Designers should follow the Stratix II external memory interface guidelines in the handbook for impedance matching, termination, and PCB stack-up to meet timing budgets.

What configuration methods does the EP2S90H484C4 support?

The EP2S90H484C4 supports JTAG (IEEE 1149.1), passive serial (PS), and EPC configuration device modes. In production, designs typically boot from an EPCS or EPC configuration flash; during development, JTAG via the Quartus II programmer is the standard load path. Configuration pins (MSEL, nCONFIG, nSTATUS, CONF_DONE) must be set according to the handbook.

工程参考数据： EP2S90H484C4 ——对比、设计指导和合规信息。

选型指南

Choose the EP2S90H484C4 when you need to maintain an existing Stratix II design, replace a defective legacy board, or target a 90,960 logic-element density in a 484-FCBGA footprint within the commercial temperature range. For industrial or outdoor applications, switch to the EP2S90F484I4N in the same package. For new designs, evaluate Stratix IV EP4SGX230 or Cyclone V 5CGXFC7 parts in compatible BGA packages to gain higher density and lower power, while accepting the cost of re-validating pin-out and I/O bank assignments. All drop-in alternatives listed above share the 484-FCBGA footprint, enabling PCB reuse.

与替代料对比

参数	本产品	EP2S90F484C4N	EP2S90F484C5N	EP2S90F484I4	EP2S90F484C3
Brand	Intel (formerly Altera)	Intel	Intel	Intel	Intel
Package	484-FCBGA 27 x 27 mm	484-FCBGA 27 x 27 mm - same	484-FCBGA 27 x 27 mm - same	484-FCBGA 27 x 27 mm - same	484-FCBGA 27 x 27 mm - same
Logic Elements	90,960	90,960	90,960	90,960	90,960
Maximum User I/O	308	308	308	308	308
On-Chip Memory (bits)	4,520,488	4,520,488	4,520,488	4,520,488	4,520,488
Speed Grade	C4	C4	C5 (faster)	I4 (industrial temp)	C3 (slower)
Operating Temperature	0 C to +85 C (Commercial)	0 C to +85 C	0 C to +85 C	-40 C to +100 C	0 C to +85 C
Process / Voltage	90 nm / 1.2 V	90 nm / 1.2 V	90 nm / 1.2 V	90 nm / 1.2 V	90 nm / 1.2 V
Lifecycle Status	Last Time Buy	Last Time Buy	Last Time Buy	Last Time Buy	Last Time Buy

关键差异点

Identical 484-FCBGA footprint across all EP2S90F484 family variants （对比 EP2S60F484 / EP2S130F484)
Speed-grade options allow post-design timing optimization （对比 EP2S90F484C3 (slowest grade))
Commercial-grade cost advantage over industrial-grade option （对比 EP2S90F484I4N (industrial-grade))

设计说明

The EP2S90H484C4 requires a multi-rail supply: VCCINT (1.2 V core), VCCPD (3.3 V), and per-bank VCCIO. Use a dedicated power plane for VCCINT with bulk decoupling (220 uF minimum) and 0.1 uF/0.01 uF high-frequency capacitors placed as close as possible to each quadrant. Pre-design power estimation in the Quartus II PowerPlay tool should be performed before PCB layout to size regulators correctly.

The 484-FCBGA package at 1.0 mm pitch requires a 4-6 layer PCB stack-up with microvia (HDI) construction. Reference the Stratix II Handbook hardware section for the recommended layer stack. Matched-length differential pair routing (within 5 ps) is required for LVDS, DDR, and DDR2 interfaces; series termination must be placed within the recommended distance of the FPGA balls to maintain signal integrity.

Estimated: at 90% utilization with all DSP blocks active, the EP2S90H484C4 may dissipate 4-6 W. The 484-FCBGA package thermal resistance is approximately 8-12 C/W (theta_JB). For commercial-temperature designs, route a sufficient copper pour beneath the package balls and ensure at least 400 LFM of airflow when sustained utilization exceeds 60%. Add a heat spreader for industrial-temperature deployments.

MSEL pins must be tied to VCCPD or GND through a 1k resistor to select the correct configuration mode (JTAG, PS, AS, FPP) - a floating MSEL causes configuration failure. Do not tie CONF_DONE or nSTATUS high; both are open-drain. For JTAG chain operation, ensure that the JTAG voltage (VCCPD) matches the JTAG programmer's reference voltage, otherwise the JTAG chain will fail to enumerate.

合规信息

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

无铅

Yes

无卤

Unknown

冲突矿物

Compliant

RoHS and lead-free compliant per Intel product page for Stratix II family. AEC-Q100 not applicable (FPGA, not automotive-qualified). Halogen-free status not explicitly stated in verified web data.

数据核验日期： 2026-09-09 ——数据由 XAIPART 元器件工程团队核验和整理

来源： Distributor, Distributor, Distributor, Octopart, Distributor, Manufacturer Datasheet, Distributor, Manufacturer Datasheet