EPC2LC20NA - 1.6Mb ISP Config PROM | Altera | PLCC-20
料号： EPC2LC20NA ⚠ 最后一次采购| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.95 | $89.50 |
| 100 | $7.65 | $765.00 |
| 500 | $6.4 | $3,200.00 |
| 1,000 | $5.5 | $5,500.00 |
EPC2LC20NA 概述
A configuration PROM (Programmable Read-Only Memory) is a non-volatile memory device that stores FPGA bitstream data and delivers it to the FPGA at power-up via a serial configuration interface. The EPC2 family belongs to the broader category of FPGA configuration memory, sitting hierarchically under programmable logic boot/storage and above generic serial PROMs. Engineers select configuration PROMs based on bitstream size, target FPGA density, voltage compatibility, and in-system reprogrammability.
Key features of the EPC2LC20NA include 1.6 Mbit density, in-system programmability via IEEE 1532 JTAG, 3.3V VCC operation, and a serial configuration data output to the target FPGA. The device supports multi-device daisy-chaining and offers short programming/erase times compared to legacy EPC1 alternatives. The PLCC-20 (9x9 mm) through-hole-compatible surface-mount package facilitates socketed programming and field-replacement workflows.
The EPC2LC20NA utilizes Altera's proven floating-gate memory cell array with on-chip charge pumps and a serial state machine that handles the configuration handshake with the host FPGA. The JTAG interface complies with IEEE Std 1149.1 boundary-scan and IEEE 1532 ISP, allowing bitstream updates without removing the device from the PCB. The internal oscillator and timing logic drive the configuration clock to the FPGA in passive serial (PS) mode, eliminating the need for an external configuration clock source.
Typical applications include boot configuration for Altera APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, and Mercury FPGA devices; industrial control boards; telecom line cards; and prototyping platforms requiring field firmware updates. The 1.6 Mb capacity comfortably fits bitstreams for mid-density FPGAs up to approximately 200,000 gates.
When designing with EPC2LC20NA, ensure the configuration mode (passive serial) of the target FPGA is selected and that the MSEL pins are set accordingly. Place a decoupling capacitor close to VCC and observe JTAG chain ordering when multiple devices share the same TAP controller.
This page synthesizes distributor stock levels, drop-in same-package alternatives, and design considerations not found in the manufacturer datasheet, providing practical guidance for legacy system maintenance and new designs targeting Altera FPGA families.
直接替换替代料： EPC2LC20NA ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPC2LC20NA （相同外形与封装尺寸） ——差异在于 Package, Memory Type, Configuration Interface, Supported FPGA Families, Mounting Type.
快速对比工具——选择替代料号进行并排对比：
EPC2LC20N
✅ 直接替换✓ 有现货
$7.4 / 个
查看数据手册 →EPC2LC20
✅ 直接替换✓ 有现货
$7.2 / 个
查看数据手册 →EPC1LC20
✅ 直接替换✓ 有现货
$7.95 / 个
查看数据手册 →EPC2LC120
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$9.95 / 个
查看数据手册 →EPC144LC20
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$7.1 / 个
查看数据手册 →EPC1LI20
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$8.5 / 个
查看数据手册 →EPC2LC20NA 最大额定值与电气特性
| Manufacturer | Altera Corporation (Intel Programmable Solutions Group) |
| 存储器类型 | Configuration PROM (Flash-based, ISP) |
| Memory Density | 1.6 Mbit |
| Operating Voltage (VCC) | 3.3 V |
| 接口 | Serial (passive-serial) data output to FPGA |
| Programmability | In-system programmable via IEEE 1532 JTAG |
| 封装 | 20-pin PLCC (9x9 mm) |
| 安装类型 | Surface Mount (PLCC socket compatible) |
| 工作温度 | -40C to +85C (industrial grade) |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury |
| JTAG Compliance | IEEE Std 1149.1 / IEEE 1532 |
| Configuration Mode | Passive Serial (PS) |
| Daisy-Chain Support | Yes |
| Recommended Companion FPGA | Altera Cyclone, FLEX 10K, APEX 20K series |
EPC2LC20NA 引脚配置
| 引脚 1 | VCC — 3.3V power supply |
| 引脚 2 | DATA — Serial configuration data output to FPGA |
| 引脚 3 | DCLK — Configuration clock output to FPGA |
| 引脚 4 | nCS — Chip select (active low) from FPGA nCONFIG |
| 引脚 5 | nSTATUS — Status signal to FPGA |
| 引脚 6 | CONF_DONE — Configuration complete signal |
| 引脚 7 | nINIT_CONF — Initiate configuration |
| 引脚 8 | nCASC — Cascade output for daisy-chain |
| 引脚 9 | TDI — JTAG test data in |
| 引脚 10 | TDO — JTAG test data out |
| 引脚 11 | TMS — JTAG test mode select |
| 引脚 12 | TCK — JTAG test clock |
| 引脚 13 | GND — Ground |
| 引脚 14 | OE — Output enable |
| 引脚 15 | nCE — Chip enable (active low) |
| 引脚 16 | RESERVED — Reserved - do not connect |
| 引脚 17 | RESERVED — Reserved - do not connect |
| 引脚 18 | RESERVED — Reserved - do not connect |
| 引脚 19 | RESERVED — Reserved - do not connect |
| 引脚 20 | GND — Ground |
典型应用
EPC2LC20NA 适用于 6 应用s: Altera Cyclone FPGA Boot Configuration, APEX 20K and ACEX 1K Configuration, FLEX 10K and FLEX 6000 Boot Memory, Multi-FPGA Daisy-Chain Configuration, Industrial Control and Factory Automation, Telecom Line Card Configuration.
Altera Cyclone FPGA Boot Configuration
The EPC2LC20NA stores the configuration bitstream for Altera Cyclone series FPGAs at system power-up, delivering data through the passive-serial interface. With 1.6 Mb density, it accommodates Cyclone EP1C3, EP1C4, and smaller Cyclone II devices whose bitstreams fit within this capacity. The 3.3V VCC matches the Cyclone core supply, eliminating level shifters. IEEE 1532 JTAG ISP enables field firmware updates without removing the device from the board, which is critical for deployed industrial and telecom systems requiring remote bitstream updates. The PLCC-20 package supports socketed programming during manufacturing and easy replacement in legacy maintenance scenarios.
推荐
APEX 20K and ACEX 1K Configuration
The EPC2LC20NA configures Altera APEX 20K and ACEX 1K FPGAs which require non-volatile boot memory. The 1.6 Mb density supports APEX 20K100, 20K200, and ACEX 1K30, 1K50 devices. The passive-serial interface is native to these families, requiring no external glue logic. Industrial-grade temperature range suits factory automation and outdoor telecom installations. JTAG ISP allows board-level reprogramming, reducing the need for physical PROM replacement during firmware iterations. The PLCC-20 footprint remains compatible with existing APEX/ACEX reference designs from Altera documentation.
推荐
FLEX 10K and FLEX 6000 Boot Memory
Legacy Altera FLEX 10K and FLEX 6000 FPGA designs use the EPC2LC20NA as primary configuration storage. The 1.6 Mb density fits FLEX 10K10, 10K30, and FLEX 6000 series bitstreams. FLEX devices use passive-serial configuration mode natively, allowing direct connection between the EPC2LC20NA and the FPGA DATA/DCLK/nCS/nCONFIG pins. The 3.3V operation is compatible with FLEX 10K VCCINT rails when properly sequenced. Maintenance of long-lifecycle industrial systems based on FLEX FPGAs often requires EPC2LC20NA replacements; this PROM's continued availability through distributors supports that requirement.
推荐
Multi-FPGA Daisy-Chain Configuration
In systems with multiple Altera FPGAs, the EPC2LC20NA can serve as one of several daisy-chained configuration PROMs, where each PROM configures one or more FPGAs in sequence. The device supports the standard Altera multi-device configuration protocol with nCASC signal hand-off between devices. This topology allows designers to mix different FPGA densities on one board, each with its own EPC2LC20NA programmed with the appropriate bitstream. The 3.3V operation and PLCC-20 package simplify board layout and allow socketed programming for production flexibility.
推荐
Industrial Control and Factory Automation
Industrial control boards with Altera FPGAs rely on the EPC2LC20NA for reliable, non-volatile boot configuration in harsh factory environments. The industrial temperature range of -40C to +85C suits outdoor cabinets, manufacturing lines, and process control systems. The in-system programmability allows remote firmware updates over JTAG, reducing truck rolls for field maintenance. The PLCC-20 package supports socketed installation, enabling fast PROM swaps during board repair. Long-term availability through distribution channels supports the 10-15 year lifecycle typical of industrial automation equipment.
推荐
Telecom Line Card Configuration
Telecom line cards based on Altera FPGAs use the EPC2LC20NA for central office-grade boot configuration where reliability and field serviceability are paramount. The device's ability to be reprogrammed via JTAG supports remote firmware updates required by carrier-grade telecom equipment. Passive-serial configuration matches the standard FPGA boot interface, simplifying PCB layout. The PLCC-20 socketed format allows field technicians to replace PROMs without soldering when provisioning different line card variants. Compliance with telecom NEBS thermal and reliability requirements is supported by the industrial temperature grade.
推荐
推荐产品汇总
工程参考数据： EPC2LC20NA ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPC2LC20N | EPC2LC20 | EPC1LC20 | EPC2LC120 | EPC144LC20 | EPC1LI20 |
|---|---|---|---|---|---|---|---|
| Package | PLCC-20 | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same | PLCC-20 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Operating Voltage | 3.3V | 3.3V | 3.3V | 3.3V (with 5V tolerant I/O) | 3.3V | 3.3V | 3.3V |
| JTAG ISP (IEEE 1532) | Yes | Yes | Yes | Limited | Yes | Yes | Limited |
| Configuration Interface | Passive Serial | Passive Serial | Passive Serial | Passive Serial | Passive Serial | Passive Serial | Passive Serial |
| Lifecycle Status | Last Time Buy | Last Time Buy | Last Time Buy | Obsolete | Last Time Buy | Obsolete | Obsolete |
| Daisy-Chain Support | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
关键差异点
- NA suffix indicates specific temperature grade （对比 EPC2LC20N)
- Full IEEE 1532 JTAG ISP support （对比 EPC1LC20)
- Native 3.3V operation （对比 EPC1LC20)
设计说明
The EPC2LC20NA requires a stable 3.3V supply on VCC (pin 1) with adequate decoupling. Place a 0.1uF ceramic decoupling capacitor as close as possible to the VCC pin, with a 10uF bulk capacitor on the supply rail nearby. During in-system programming, peak currents may reach 50-100 mA; ensure the regulator can supply this transient. Power sequencing: VCC must be stable before nCONFIG rises to initiate configuration. The absolute maximum DC input is -0.3V; during transitions inputs may undershoot to -2.0V for periods shorter than 20 ns under no-load conditions.
Place the EPC2LC20NA as close to the target FPGA as possible to minimize the trace length on DATA and DCLK signals. Use a series termination resistor (33-68 ohm) on DCLK if the trace exceeds 50 mm to dampen reflections. JTAG signals (TDI, TDO, TMS, TCK) should be routed together with similar trace lengths to maintain signal integrity at JTAG clock rates. Keep the PROM away from switching power supply inductors and high-frequency clocks to avoid coupling noise into the configuration interface.
When using EPC2LC20NA as a drop-in for EPC1LC20, verify that the target FPGA's MSEL pins are configured for passive-serial mode and that the nINIT_CONF timing matches. Do not connect RESERVED pins (16-19) - leave them floating per datasheet. For JTAG ISP, ensure the JTAG chain order is correct when multiple devices share the TAP controller. Verify that the Quartus programmer software version supports the EPC2 device family; older Quartus versions may require explicit device selection in the programmer dialog.
合规信息
Compliance information not explicitly stated in verified web data. Altera (now Intel PSG) typically produced configuration PROMs compliant with RoHS for lead-free assembly, but verify with current manufacturer documentation before use in compliant designs.