HI5766KCB - 10-Bit 60MSPS CMOS ADC | Renesas | 28-SOIC
料号： HI5766KCB ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $14.85 | $14.85 |
| 10 | $13.4 | $134.00 |
| 100 | $11.75 | $1,175.00 |
| 500 | $10.2 | $5,100.00 |
| 1,000 | $8.95 | $8,950.00 |
HI5766KCB 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous analog voltage and produces a discrete digital code proportional to the input level. Within the broader taxonomy, the HI5766KCB is a successive-stage pipelined ADC, a sub-type of Nyquist-rate data converters that sit between precision SAR ADCs (slow, high-resolution) and flash ADCs (fast, low-resolution). Pipelined ADCs occupy the middle ground: they offer high sampling rates (tens to hundreds of MSPS) at moderate resolution (8-14 bits) by cascading low-resolution stages, each stage producing a residue amplified for the next conversion stage. The HI5766KCB inherits this pipelined architecture but adds an internal sample-and-hold and CMOS-compatible digital outputs to simplify host interface design.
Key features include 60 MSPS maximum sampling rate, 10-bit resolution, single 5V analog supply operation, CMOS digital outputs, internal sample-and-hold, and a fully differential analog input path. The pipelined architecture provides low latency and excellent spurious-free dynamic range for IF-sampling applications. Power dissipation is typically modest for the speed class, and digital outputs are directly compatible with 5V or 3.3V logic families depending on the supply configuration.
Typical applications include professional video digitisation, IF sampling in communications receivers, digital oscilloscope front-ends, medical imaging preprocessing, and CCD/camera pixel array readout. The 10-bit resolution and 60 MSPS throughput are well-suited to standard-definition broadcast video (ITU-R BT.601) and intermediate-frequency undersampling in digital radio designs.
When designing with this device, ensure the analog input common-mode voltage is biased within the converter's input range and that the external reference decoupling is low-ESR. PCB layout should keep analog input traces short and symmetrical, with a dedicated ground plane under the analog section to preserve spurious-free dynamic range.
This page synthesises distributor pricing, drop-in alternative MPNs in the same 28-SOIC footprint, and practical PCB/thermal notes that the manufacturer datasheet alone does not present. Cross-brand equivalents from ADI and Texas Instruments that are pin-compatible in the 28-SOIC package are summarised below.
直接替换替代料： HI5766KCB ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： HI5766KCB （相同外形与封装尺寸） ——差异在于 Package, Architecture, Input Type, Resolution, Data Interface.
快速对比工具——选择替代料号进行并排对比：
HI5766KCAZ
✅ 直接替换✓ 有现货
$5.6 / 个
查看数据手册 →AD9200ARUZ
✅ 直接替换📋 参考替代料（不在目录中）
ADS901E/1K
✅ 直接替换✓ 有现货
$2.59 / 个
查看数据手册 →ADS901E/1K
✅ 直接替换✓ 有现货
$2.59 / 个
查看数据手册 →ADS901E/1KG4
✅ 直接替换✓ 有现货
$4.12 / 个
查看数据手册 →ADS7841PBG4
✅ 直接替换✓ 有现货
$4.12 / 个
查看数据手册 →HI5766KCB 最大额定值与电气特性
| 分辨率 | 10 bit |
| 采样率 | 60 MSPS |
| Architecture | Pipelined |
| Number of Channels | 1 |
| Input Type | Differential (single-ended capable) |
| Analog Supply Voltage | 5 V |
| Digital Output Type | CMOS |
| 封装 | 28-pin SOIC (Wide) |
| Sample-and-Hold | Internal |
| 工作温度 | 0C to +70C (commercial) |
| Process | CMOS |
| 安装类型 | Surface Mount |
| 输入电压范围 | -0.5 V to 0.5 V (differential, per datasheets.com snippet) |
HI5766KCB 引脚配置
| 引脚 1 | AVDD — Analog +5V supply |
| 引脚 2 | AVDD — Analog +5V supply |
| 引脚 3 | AGND — Analog ground |
| 引脚 4 | REFT — Top reference voltage (decoupling) |
| 引脚 5 | REFB — Bottom reference voltage (decoupling) |
| 引脚 6 | AIN+ — Differential analog input positive |
| 引脚 7 | AIN- — Differential analog input negative |
| 引脚 8 | AGND — Analog ground |
| 引脚 9 | AGND — Analog ground |
| 引脚 10 | CLK — Sampling clock input |
| 引脚 11 | DGND — Digital ground |
| 引脚 12 | DVDD — Digital supply (3.3V or 5V) |
| 引脚 13 | D0 — Digital output bit 0 (LSB) |
| 引脚 14 | D1 — Digital output bit 1 |
| 引脚 15 | D2 — Digital output bit 2 |
| 引脚 16 | D3 — Digital output bit 3 |
| 引脚 17 | D4 — Digital output bit 4 |
| 引脚 18 | D5 — Digital output bit 5 |
| 引脚 19 | D6 — Digital output bit 6 |
| 引脚 20 | D7 — Digital output bit 7 |
| 引脚 21 | D8 — Digital output bit 8 |
| 引脚 22 | D9 — Digital output bit 9 (MSB) |
| 引脚 23 | DGND — Digital ground |
| 引脚 24 | DGND — Digital ground |
| 引脚 25 | OE — Output enable (active high) |
| 引脚 26 | AGND — Analog ground |
| 引脚 27 | AVDD — Analog +5V supply |
| 引脚 28 | AVDD — Analog +5V supply |
典型应用
HI5766KCB 适用于 6 应用s: Standard-Definition Video Digitisation, IF Sampling in Communications Receivers, Digital Oscilloscope Front-End, Medical Imaging Preprocessing, CCD/Camera Pixel Array Readout, Industrial Process Control Data Acquisition.
Standard-Definition Video Digitisation
The HI5766KCB's 10-bit resolution and 60 MSPS throughput align directly with ITU-R BT.601 standard-definition digital video, which requires 8-bit minimum at 27 MSPS. Placed at the analog front-end of a video capture board following anti-alias filtering, the converter samples composite or component video at 27 MHz (4:2:2) or 54 MHz oversampled modes. Its CMOS outputs feed an FPGA or dedicated video encoder with minimal glue logic. Compared to a modern 12-bit video ADC, the 10-bit resolution limits dynamic range to ~60 dB but is more than adequate for surveillance, broadcast monitoring, and industrial machine-vision pipelines.
推荐
IF Sampling in Communications Receivers
The HI5766KCB's pipelined architecture and 60 MSPS sampling rate make it a strong fit for intermediate-frequency (IF) undersampling in digital radio receivers and spectrum analysers. When placed at the output of a 21.4 MHz or 44 MHz IF strip, the ADC delivers 10-bit amplitude resolution with sufficient SFDR for narrow-band demodulation. The fully differential input rejects common-mode noise from upstream mixers, and CMOS outputs feed directly into a digital down-converter (DDC) or FPGA. Engineers should evaluate SFDR at the target IF frequency against published datasheet curves; consider the AD9200 for higher SFDR-critical paths.
推荐
Digital Oscilloscope Front-End
For low-bandwidth digital oscilloscopes (10-30 MHz analog bandwidth) and data-acquisition front-ends, the HI5766KCB provides 60 MSPS sampling suitable for 10 MHz real-time capture with x4 oversampling. Its pipelined architecture adds deterministic 5-clock latency that is trivial for post-trigger acquisition but requires careful compensation for equivalent-time sampling modes. The CMOS parallel outputs integrate cleanly with FPGA-based trigger logic. For higher-bandwidth scopes, a faster 100+ MSPS ADC such as the AD9226 family is required.
推荐
Medical Imaging Preprocessing
In medical ultrasound front-ends and patient-monitoring acquisition boards, the HI5766KCB's 10-bit resolution digitises pre-processed analog signals (post-TGC amplifier, post-beamformer) at sufficient rate for envelope detection and digital filtering. The 5V supply integrates with legacy medical instrumentation rails, and the SOIC package simplifies hand-prototyping. Differential inputs reject common-mode pickup from long patient cables. For higher-resolution imaging modalities such as MRI or CT, a 12-16 bit ADC such as ADS1256 is required.
推荐
CCD/Camera Pixel Array Readout
Industrial line-scan and area-scan cameras digitising CCD or CMOS sensor analog outputs benefit from the HI5766KCB's 60 MSPS throughput and 10-bit dynamic range. Placed at the output of the analog front-end amplifier, the ADC samples each pixel row at pixel-clock rates from 10 to 50 MHz with correlated double-sampling support. The 28-SOIC footprint simplifies multi-channel PCB layouts when several ADCs are paralleled for colour Bayer pattern capture. For higher-end machine-vision, the 12-bit ADS805E provides additional dynamic range.
推荐
Industrial Process Control Data Acquisition
The HI5766KCB serves as the high-speed digitiser in industrial process-control DAQ cards, sampling 4-20 mA loop signals after current-to-voltage conversion and signal conditioning. Its 60 MSPS throughput enables oversampling of multiplexed analog channels for improved effective resolution (averaging four samples yields 12 effective bits). The 28-SOIC commercial temperature range (0-70C) suits enclosure-mounted industrial PCs. The CMOS outputs interface cleanly with industrial FPGAs and backplane logic. For wider temperature range designs, the HI5766KCAZ industrial-grade variant is recommended.
推荐
推荐产品汇总
工程参考数据： HI5766KCB ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | HI5766KCAZ | AD9200ARUZ | ADS901E | ADS7841PBG4 |
|---|---|---|---|---|---|
| Package | 28-SOIC (Wide) | 28-SOIC (Wide) - same | 28-SOIC (Wide) - same | 28-SOIC (Wide) - same | 28-SOIC (Wide) - same |
| Brand | Renesas Electronics | Renesas Electronics | Analog Devices | Texas Instruments | Texas Instruments |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit |
| Sampling Rate | 60 MSPS | 60 MSPS | 50 MSPS | 20-30 MSPS | 200 kSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | SAR |
| Analog Supply | 5 V | 5 V | 5 V | 5 V | 5 V |
| Digital Output Type | CMOS parallel | CMOS parallel | CMOS parallel | CMOS parallel | CMOS/Serial |
| Lifecycle Status | NRND | NRND | Obsolete (use AD9200ARUZ-REEL) | Active | NRND |
关键差异点
- Higher maximum sampling rate than AD9200 （对比 AD9200ARUZ)
- Drop-in 28-SOIC footprint across multiple vendors （对比 ADS901E)
- Higher throughput than ADS7841PBG4 at same resolution （对比 ADS7841PBG4)
设计说明
Layout the 28-SOIC footprint with a continuous analog ground plane beneath the analog input pins (AIN+ / AIN-, REFT, REFB) and a separate digital ground return for the CMOS output bus (D0-D9) and CLK. Join the two grounds at a single point near the AGND/DGND pin pair to avoid digital switching currents corrupting the analog reference. Place 0.1 uF ceramic decoupling capacitors within 5 mm of each AVDD pin, and add a 10 uF tantalum bulk capacitor on the AVDD rail close to the IC. Keep analog input traces symmetrical and matched-length, and route the CLK trace perpendicular to the analog inputs to minimise clock-feedthrough.
Drive the CLK input from a low-jitter clock source (jitter < 5 ps RMS) to preserve aperture sensitivity and signal-to-noise ratio at 60 MSPS. If the application requires undersampling of an IF signal, calculate SNR degradation as 20*log10(1/(2*pi*f_IF*t_jitter)) and ensure the jitter budget fits the target SNR. Place a 100 ohm series damping resistor at the CLK pin if the source impedance is below 50 ohm to suppress reflections. Verify timing margins against the published t_HOLD and t_SETUP specifications in the Renesas datasheet.
Common pitfalls with the HI5766KCB include: (1) failing to bias the AIN+ / AIN- common-mode voltage within the converter's input range (typically 2.5V for 5V supply), which clips or distorts the analog input; (2) leaving REFT and REFB pins without the recommended decoupling network, which degrades linearity and INL; (3) driving the CMOS outputs beyond their rated fan-out (> 10 LS-TTL loads), which slows edges and adds digital noise to the analog section; (4) ignoring the 5-clock pipeline latency in real-time control loops. Reference the Renesas application note for the recommended input common-mode bias circuit.
合规信息
MSL rating, RoHS, REACH, lead-free, halogen-free, and conflict-minerals status were not present in the provided web data - all set to unknown. AEC-Q100 not applicable as this is a commercial-grade ADC.