KSZ9021RL Gigabit Ethernet PHY, RGMII, 64-LQFP | Microchip
料号： KSZ9021RL ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.7042 | $8.70 |
| 10 | $8.7042 | $87.04 |
| 100 | $8.7042 | $870.42 |
| 500 | $8.7042 | $4,352.10 |
| 1,000 | $8.7042 | $8,704.20 |
KSZ9021RL 概述
A Gigabit Ethernet PHY, also called an Ethernet physical-layer transceiver, sits between a network media-access controller and the copper cable. It converts digital MAC data into electrical signals for transmission and converts received cable signals back into digital data. The KSZ9021RL is therefore positioned within the Ethernet interface hierarchy: network controller, interface transceiver, PHY, Ethernet transceiver, interface IC, and semiconductor.
The KSZ9021 family provides RGMII support and a low-jitter 125 MHz reference-clock output on CLK125_NDO. That clock can provide a lower-cost reference-clock alternative for RGMII MACs that otherwise require a separate 125 MHz crystal or oscillator. Auto-negotiation follows IEEE 802.3 Clause 28 and selects the highest common operating mode between connected link partners. Its three-speed support allows one physical network interface to handle 10 Mb/s, 100 Mb/s, and 1000 Mb/s links.
The KSZ9021RL is packaged in a 64-pin lead-free E-LQFP, while related KSZ9021RN, KSZ9021GN, and KSZ9021GQ order codes use different package configurations and pin counts. Package identity is essential during substitution: the 48-pin QFN RN version and the other family packages cannot be treated as pin-compatible replacements for the RL device. Although all use the KSZ9021 name, footprint and pin assignment must be checked before redesigning or sourcing a substitute.
Typical applications include industrial Ethernet controllers, embedded network equipment, set-top boxes, digital media systems, and communication equipment using an RGMII-capable MAC. The device is appropriate when the design requires integrated triple-speed copper Ethernet, auto-negotiation, and a shared MAC interface rather than a purely passive or single-speed physical layer.
Layout should treat the analog PHY and magnetics interface as a high-speed, sensitive signal path. Keep copper traces controlled, provide the decoupling and analog-supply arrangements required by the manufacturer datasheet, and route differential pairs away from noisy switching nodes. Verify magnetics, cable, termination, and thermal conditions against the complete system design rather than treating the PHY as a standalone digital component.
This page combines verified manufacturer and distributor information with package-specific selection guidance, pricing, and practical Ethernet design considerations. It does not infer unreleased electrical limits or present package variants as drop-in substitutes when their footprints differ.
直接替换替代料： KSZ9021RL ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： KSZ9021RL （相同外形与封装尺寸） ——差异在于 Package, Supply Voltage.
快速对比工具——选择替代料号进行并排对比：
该产品暂无直接替换替代料。
请求替代料KSZ9021RL 规格参数
| Product Type | Single-port Gigabit Ethernet physical-layer transceiver |
| Supported Ethernet Speeds | 10 Mb/s, 100 Mb/s, and 1000 Mb/s |
| Supported Physical Standards | 10BASE-T, 100BASE-TX, and 1000BASE-T |
| Cable Medium | Standard CAT-5 unshielded twisted pair |
| MAC Interface | RGMII |
| 电源电压 | 3.3 V |
| Reference Clock Output | 125 MHz on CLK125_NDO |
| Auto-Negotiation Protocol | IEEE 802.3 Clause 28 |
| 封装 | 64-pin lead-free E-LQFP |
| 引脚数量 | 64 pins |
| 安装类型 | Surface mount |
| Maximum Link Speed | 1000 Mbps |
| Transceiver Configuration | Single port |
| Lead-Free Status | Lead-free |
KSZ9021RL 64-pin lead-free e-lqfp 引脚配置指南
KSZ9021RL（64-pin lead-free e-lqfp 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： KSZ9021RL.
请参阅 数据手册 以查看完整引脚配置。
典型应用
KSZ9021RL 适用于 6 应用s: Industrial Ethernet Control Equipment, Embedded Linux Network Appliances, Digital Media and Set-Top Platforms, Communication Gateways, Network Test and Measurement Products, Networked Sensors and Smart Equipment.
Industrial Ethernet Control Equipment
The KSZ9021RL fits an RGMII-capable controller that must connect industrial equipment through one copper Ethernet port while supporting 10, 100, or 1000 Mb/s links. Its verified IEEE 802.3 Clause 28 auto-negotiation allows the PHY and link partner to select the highest common mode, reducing fixed-speed configuration requirements. The device pairs a 3.3 V supply with a 125 MHz CLK125_NDO reference option, but the enclosure temperature, EMC limits, industrial qualification, and magnetics still require system-level verification. A controlled Ethernet layout, compliant magnetics, and verified surge protection are essential for factory-floor equipment.
推荐
Embedded Linux Network Appliances
KSZ9021RL is appropriate for an embedded Linux platform whose application processor or communications controller exposes RGMII and needs legacy-to-Gigabit Ethernet compatibility. The transceiver supports 10BASE-T, 100BASE-TX, and 1000BASE-T on one port, while auto-negotiation adapts the link without forcing the software stack to know the cable partner's capability. The optional 125 MHz CLK125_NDO output may simplify reference-clock sourcing for a suitable RGMII MAC. Software timing configuration, PHY reset sequencing, magnetics selection, and Linux driver support must be evaluated separately because those details are not included in the supplied verification data.
推荐
Digital Media and Set-Top Platforms
The KSZ9021RL can serve a digital media or set-top design that needs a standards-compatible copper Ethernet connection alongside RGMII-based internal signaling. Its verified triple-speed support covers 10BASE-T through 1000BASE-T, while Clause 28 auto-negotiation improves interoperability with older switches and endpoint devices. The 64-pin E-LQFP package is larger than the 48-pin KSZ9021RN QFN option, so board-area planning and assembly capability should be considered early. Keep the PHY-to-magnetics section compact, observe the manufacturer's reference layout, and validate return loss and radiated emissions before production.
推荐
Communication Gateways
KSZ9021RL fits a communication gateway that bridges an embedded control plane to a 10/100/1000 Mb/s copper network. Supporting all three rates through one PHY allows the gateway to connect to both legacy plant equipment and modern Gigabit infrastructure. RGMII provides the digital interface to the host MAC, and the 125 MHz reference output may reduce external clock cost when supported by the host design. The principal engineering concerns are signal integrity across the RGMII bus, magnetics isolation, analog supply quality, reset timing, and cable surge events. Use the official RL/RN datasheet and its reference implementation for exact values rather than extrapolating from other family packages.
推荐
Network Test and Measurement Products
The KSZ9021RL is suitable for test equipment or protocol analyzers that need a repeatable copper-link endpoint with support for 10, 100, and 1000 Mb/s operation. Auto-negotiation helps validate interoperability with different Ethernet link partners, while RGMII provides a direct digital connection to a controller or capture engine. Because the PHY itself does not create test traffic, instrumentation functions remain the responsibility of the MAC and application processor. Designers should budget board space for the 64-pin E-LQFP, magnetics, and protection components, and should verify line-side layout against the manufacturer reference design to prevent jitter or EMC regressions.
推荐
Networked Sensors and Smart Equipment
KSZ9021RL can provide copper Ethernet connectivity in a networked sensor controller or smart piece of equipment that already has an RGMII-capable host. The 10/100/1000 Mb/s support allows installation on different network generations, and the 125 MHz CLK125_NDO option can support an appropriate host clock architecture. Smart-equipment designs must still check low-power behavior, startup time, isolation, environmental temperature, and cable reach using unverified values from the complete datasheet. If the controller does not support RGMII, select a MAC/PHY combination with a matching parallel interface rather than adding unsupported glue logic.
推荐
推荐产品汇总
工程参考数据： KSZ9021RL ——对比、设计指导和合规信息。
选型指南
关键差异点
- Integrated three-speed copper Ethernet （对比 KSZ9021RN)
- Dedicated 125 MHz reference-clock output （对比 KSZ9021GN)
- RGMII integration （对比 KSZ9021GQ)
设计说明
Treat the RGMII interface as a timing-sensitive digital bus and the line-side network section as a controlled-impedance analog design. Place the PHY and Ethernet magnetics according to the official KSZ9021RL/RN reference layout, minimize stub lengths, use the specified decoupling, and keep the 125 MHz clock distribution clean. Do not infer the RN package layout or pin values for the RL device because their pin counts and footprints differ.
Use the manufacturer reference design to select PHY, magnetics, termination, and protection components, and preserve the recommended copper geometry around the line-side interface. Keep switching regulators, clocks, and high-current paths away from sensitive analog and differential network areas. Validate return loss, insertion loss, radiated emissions, and immunity in the final enclosure and cable configuration rather than relying only on schematic simulation.
The most common replacement mistake is treating KSZ9021RL, KSZ9021RN, KSZ9021GN, and KSZ9021GQ as interchangeable. The verified Microchip information identifies a 64-pin E-LQFP for RL, a 48-pin QFN for RN, a 64-pin QFN for GN, and a 128-pin PQFP for GQ. Confirm the exact suffix, pinout, power requirements, and land pattern before layout release or substitution.
合规信息
Microchip identifies KSZ9021RL as lead-free. RoHS, REACH, halogen-free, and conflict-minerals statuses were not stated in the supplied verified data.
