LAN91C113-NS - 100Mbps Ethernet Controller | Microchip
料号： LAN91C113-NS ✓ 量产中LAN91C113-NS 概述
An Ethernet controller is an interface integrated circuit that connects a digital processor or system bus to an Ethernet network. The LAN91C113 belongs to the Ethernet interface controller category, which combines a media access controller, physical-layer transceiver, and host-facing parallel interface. This integration can reduce the number of external network components while providing a standardized 10/100 Ethernet connection for embedded equipment.
The principal operating characteristics are a 100 Mbps data rate, compliance with IEEE 802.3 and IEEE 802.3u, MII host connectivity, and a 3.3 V supply. The listed supply current is 100 mA, while the operating temperature extends from 0°C to 85°C. These specifications position the device for industrial, communications, and embedded systems that use a parallel host interface instead of a serial media interface.
The 128-QFP package provides the physical footprint and pin count needed for a substantial mixed-signal Ethernet interface. Because the MAC and PHY are integrated, PCB design requires careful separation of Ethernet signal routing, supply distribution, and grounding. The parallel MII interface should be routed according to the manufacturer's recommended layout and timing guidance to limit data-integrity and electromagnetic-interference issues.
Typical uses include industrial Ethernet control equipment, embedded network gateways, data acquisition systems, print servers, and communication controllers. In each case, the device serves as the link between a host processor and a 10/100 Ethernet network. Its 3.3 V operation and commercial temperature range support compact systems where 100 Mbps connectivity is sufficient and a dedicated PHY is undesirable.
Designers should confirm pin functions, timing, clocking, magnetics, and decoupling directly against the manufacturer datasheet before layout release. Particular attention should be given to MII clock timing, PHY termination, analog supply routing, and the separation between Ethernet traces and sensitive digital signals. These controls are more important than raw headline speed when establishing reliable network performance.
This page organizes the LAN91C113-NS specifications, sourcing information, interface context, application guidance, and same-package replacement considerations. It also identifies which technical details require confirmation from the manufacturer documentation before a new PCB is released.
直接替换替代料： LAN91C113-NS ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LAN91C113-NS （相同外形与封装尺寸） ——差异在于 Package.
LAN91C113
✅ 直接替换📋 参考替代料（不在目录中）
LAN91C113-NU
✅ 直接替换联系询价
查看数据手册 →LAN91C112
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LAN91C111
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LAN91C116
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LAN91C113-NS 规格参数
| Device Type | Ethernet controller with integrated MAC and PHY |
| Ethernet Data Rate | 100 Mbps |
| Supported Ethernet Standards | IEEE 802.3, IEEE 802.3u |
| Physical Layer | 10/100 Base-T/TX PHY |
| Host Interface | 16-bit parallel MII |
| Minimum Supply Voltage | 2.97 V |
| Nominal Supply Voltage | 3.3 V |
| 电源电流 | 100 mA |
| 封装 | 128-QFP |
| 安装类型 | Surface mount |
| 工作温度 | 0°C to 85°C |
| Component Classification | Controller interface IC |
| Protocol | Ethernet |
| RoHS 状态 | Compliant |
| Lead-Free Status | Compliant |
| Manufacturing Country | China |
LAN91C113-NS 128-qfp 引脚配置指南
LAN91C113-NS（128-qfp 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： LAN91C113-NS.
请参阅 数据手册 以查看完整引脚配置。
典型应用
LAN91C113-NS 适用于 6 应用s: Industrial Ethernet Control Equipment, Embedded Network Gateway, Data Acquisition System, Print and Network Peripheral, Communication and Protocol Gateway, Compact Embedded Network Appliance.
Industrial Ethernet Control Equipment
The LAN91C113-NS suits industrial controllers that need a 100 Mbps Ethernet connection while operating from 3.3 V. Its integrated 10/100 Base-T/TX PHY removes the need for a separate physical-layer transceiver, while the 16-bit MII interface provides a direct path to a capable host processor. The stated 0°C to 85°C range supports many indoor industrial products. Design around the manufacturer reference circuit, including proper supply decoupling, Ethernet magnetics, and MII timing. Although 100 Mbps is sufficient for supervisory control, diagnostics, configuration exchange, and moderate data transfer, it should not be selected where a production line must aggregate multiple high-rate sensors into a Gigabit uplink.
推荐
Embedded Network Gateway
A gateway can use the LAN91C113-NS to bridge a low-power embedded processor to a 10/100 Ethernet LAN without adding a separate PHY. The controller supports 100 Mbps traffic, a parallel MII interface, and a 3.3 V supply, allowing it to coexist with modern embedded processing platforms. Integrated MAC and PHY functions also simplify the physical-layer bill of materials. The main engineering constraint is MII host support: the processor must provide the required data, control, and clock signals, and the firmware must match the LAN91C113 configuration. This makes the device most appropriate for equipment that is designed around an MII-capable host rather than one designed initially for RMII or SPI Ethernet.
推荐
Data Acquisition System
The LAN91C113-NS can provide the network path for a distributed measurement system that collects samples locally and forwards them over a 10/100 network. Its 100 Mbps rate is adequate for moderate-rate measurement data, status information, and remote commands, while the integrated PHY reduces external circuit complexity. The 3.3 V supply is useful for systems already operating at that rail. For designs with high sample rates, burst transfers, or large diagnostic files, use buffering and traffic shaping so Ethernet transfers do not disrupt timing-sensitive acquisition. Validate the MII timing, clock source, and software driver under sustained traffic rather than relying only on nominal throughput.
推荐
Print and Network Peripheral
LAN91C113-NS is appropriate for a legacy or industrial print peripheral that needs a direct 10/100 Ethernet connection and uses a parallel MII host bus. The controller's integrated MAC and PHY reduce the board area required by a discrete Ethernet implementation, and its 100 Mbps rate matches common print-control and job-transfer workloads. A 3.3 V system can power the controller from the same rail as compatible host logic. Before using it in a new design, confirm that the chosen host processor supports MII and that its Ethernet driver includes the LAN91C113 register model. Legacy equipment upgrades may also require preservation of an existing connector, magnetics, and isolation scheme.
推荐
Communication and Protocol Gateway
The LAN91C113-NS can terminate a 10/100 Ethernet link in equipment that translates among industrial, serial, or embedded protocols. Its 100 Mbps capacity handles moderate telemetry and command traffic, while the integrated PHY simplifies the physical network interface. The 16-bit parallel MII bus may be advantageous when the host processor was designed with ample parallel I/O but no native RMII interface. System partitioning becomes important because the controller and external transceiver magnetics must coexist with sensitive circuitry. Use controlled-impedance routing, uninterrupted reference planes, and isolated Ethernet interfaces where required by the end product. The 0°C to 85°C range covers many indoor communications products.
推荐
Compact Embedded Network Appliance
A compact appliance can use the LAN91C113-NS to provide network management and service access while the main processor performs its primary function. The 128-QFP package contains a complete 10/100 MAC and PHY, reducing the external component count compared with separate Ethernet components. The interface remains best suited to an MII-capable processor because the device does not present the smaller pin count associated with serial-media interfaces. Designers should allocate copper and magnetics for the Ethernet physical interface, separate analog and digital supplies where the datasheet recommends it, and verify startup and link behavior under the system's power sequence. For installations expecting sustained Gigabit traffic, select a Gigabit-class PHY instead.
推荐
推荐产品汇总
工程参考数据： LAN91C113-NS ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LAN91C113 | LAN91C113-NU | LAN91C112 | LAN91C111 | LAN91C116 |
|---|---|---|---|---|---|---|
| Package | 128-QFP | 128-QFP | 128-QFP | 128-QFP | 128-QFP | 128-QFP |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Ethernet Data Rate | 100 Mbps | 100 Mbps | 100 Mbps | 100 Mbps | 100 Mbps | 100 Mbps |
| Nominal Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
关键差异点
- Combines a 100 Mbps MAC and 10/100 PHY in one controller （对比 KSZ8001SL-TR)
- Provides a 16-bit parallel MII host interface （对比 KSZ9131RNXC)
- Supports the same 100 Mbps rate as the nearest family alternatives （对比 LAN91C113-NU)
设计说明
Route the Ethernet differential pairs as a controlled-impedance pair and keep them on a continuous reference plane. Follow the manufacturer recommended magnetics and termination arrangement because the integrated PHY does not remove the need for an external Ethernet isolation or coupling network. Keep the MII bus traces short and avoid routing them beneath switching regulators, clock generators, or other high-current paths.
Validate MII timing at the host connector and the Ethernet controller pins with the production reference clock. MII is a source-synchronous parallel interface, so clock skew, trace-length mismatch, and loading can affect data integrity even though the nominal link rate is only 100 Mbps. Use the datasheet timing tables and probe the actual assembled board; software-only testing may conceal marginal hardware behavior.
Decouple the controller close to its supply pins and preserve the separation between analog and digital supply paths recommended by the manufacturer. The listed 100 mA supply current should be included in the 3.3 V rail budget, together with Ethernet magnetics, PHY-related circuitry, and host-interface loading. Confirm whether the selected board requires an isolated Ethernet interface and include its power implications in the system thermal design.
Do not treat any same-package LAN91C11x device as a substitute until its pin names, MII behavior, reference-clock requirements, memory map, interrupt structure, and driver support have been compared. Package and data-rate matching are necessary but not sufficient. A replacement should also be checked for startup behavior, PHY register differences, temperature limits, and changes in the recommended external network circuit.
合规信息
A product listing identifies the LAN91C113-NS as RoHS3 compliant with a lead-free status. No separate REACH, halogen-free, or conflict-minerals statement was identified.
