LTC2140IUP-14 - 14-Bit 25Msps Dual ADC | Analog Devices | 64-QFN
料号： LTC2140IUP-14 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $36.97 | $36.97 |
| 10 | $33.2 | $332.00 |
| 100 | $30.5 | $3,050.00 |
| 500 | $28.4 | $14,200.00 |
| 1,000 | $27.71 | $27,710.00 |
LTC2140IUP-14 概述
A pipelined ADC is a high-speed converter architecture that resolves one or two bits per internal stage and combines a sample-and-hold front end with multi-stage switched-capacitor gain/flash blocks; it is the workhorse architecture for communications baseband, ultrasound beamforming, and digital oscilloscope digitizers where multi-Msps rates are required. The LTC2140 sits in the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Compared with successive-approximation (SAR) ADCs, pipelined parts deliver far higher sample rates at the cost of pipeline latency, while still offering multi-bit-per-stage quantization.
Key features include a flexible digital output interface supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS modes, and a separate output supply rail that lets the CMOS swing range from 0.4V to 1.8V independent of the analog 1.8V core. Programmable operating modes are accessible through either a parallel interface or a more flexible serial interface. The two channels sample simultaneously, which is essential for I/Q demodulators, phased-array receivers, and multi-channel data acquisition systems.
Typical applications span communications infrastructure (IF/RF digitizers, diversity receivers, multi-antenna baseband), portable and battery-powered imaging, medical ultrasound front ends, industrial inspection cameras, and handheld or bench-top test instrumentation. Two matching channels let the part replace a dual-board ADC+amplifier chain in space-constrained designs.
When designing with this part, allocate adequate copper area to the exposed pad for thermal relief (the dual 25 Msps core dissipates non-trivial power at full rate), route the LVDS/CMOS outputs with controlled impedance, and decouple OVDD and AVDD separately. The serial programming interface is recommended when the full feature set (output mode, gain, channel calibration) is required.
This page synthesizes distributor stock and pricing, drop-in and same-package alternatives, and practical design notes that are not duplicated on the Analog Devices datasheet.
直接替换替代料： LTC2140IUP-14 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2140IUP-14 （相同外形与封装尺寸） ——差异在于 Architecture, Package, Resolution, Sample Rate.
快速对比工具——选择替代料号进行并排对比：
LTC2141IUP-14
✅ 直接替换📋 参考替代料（不在目录中）
LTC2142IUP-14
✅ 直接替换✓ 有现货
$34.71 / 个
查看数据手册 →LTC2140CUP-14
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
LTC2140IUP-14#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2140IUP-14 最大额定值与电气特性
| 分辨率 | 14 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 25 Msps per channel |
| Architecture | Pipelined, with S/H-ADC front end |
| Input Type | Differential |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Transition Noise | 1.2 LSB RMS |
| Missing Codes Over Temperature | None guaranteed |
| Output Interface | Parallel CMOS (full-rate or DDR), DDR LVDS |
| Output Supply Range (OVDD) | 0.4 V to 1.8 V (separate from AVDD) |
| Programming Interface | Parallel or serial SPI |
| 封装 | 64-pin QFN (9x9 mm) with exposed pad |
| 安装类型 | Surface Mount |
| 工作温度 | -40 C to +85 C (industrial grade, 'I' suffix) |
| RoHS 状态 | Compliant (PBF suffix) |
LTC2140IUP-14 64-pin qfn (9x9 mm) with exposed pad 引脚配置指南
LTC2140IUP-14（64-pin qfn (9x9 mm) with exposed pad 封装）的引脚配置。 该模拟元件具有输入、输出和电源引脚。请参阅制造商数据手册以了解失调调零、补偿和使能引脚配置。适用于信号调理和放大器电路。
暂无详细引脚数据： LTC2140IUP-14.
请参阅 数据手册 以查看完整引脚配置。
典型应用
LTC2140IUP-14 适用于 6 应用s: Communications Baseband Digitizing, Portable Medical Ultrasound, Industrial Imaging and Inspection, Handheld Test and Measurement, Software-Defined Radio IF Sampling, Multi-Channel Data Acquisition Systems.
Communications Baseband Digitizing
The LTC2140IUP-14 is well-suited to baseband digitizing in diversity receivers and multi-antenna base stations. The two simultaneously-sampling 14-bit channels maintain ±1 LSB INL and 1.2 LSBRMS transition noise, preserving ENOB around 12 bits at Nyquist - enough for clean demodulation of QAM and OFDM signals where EVM is dominated by the converter. The LVDS DDR output mode drives an FPGA's deserializer directly with low EMI. Power is the lowest in its family (roughly 30% below the 65 Msps LTC2142IUP-14), so the part helps base-station radios stay within their thermal envelope while the second channel absorbs a diversity or MIMO stream.
推荐
Portable Medical Ultrasound
Handheld ultrasound carts and wireless probe designs benefit from the LTC2140IUP-14's dual simultaneous-sampling 25 Msps rate and low per-channel power. Two matched channels let one IC digitize a transmit/receive pair, halving board area versus two single-channel ADCs. Per Analog Devices datasheet 21421014fa, the differential inputs pair directly with active termination and a low-noise ADC driver op-amp, while the CMOS DDR outputs feed an FPGA that beamforms the channels. The exposed pad provides enough thermal mass to keep junction temperature in spec at sustained transmit duty cycles typical of color-flow Doppler imaging.
推荐
Industrial Imaging and Inspection
Multi-camera machine-vision and high-speed line-scan imaging systems use the LTC2140IUP-14 to digitize two synchronized video channels at up to 25 Msps each, capturing both odd/even fields of a dual-output sensor or two synchronized cameras. The flexible OVDD supply (0.4 V to 1.8 V) lets the CMOS outputs match the FPGA I/O voltage directly, avoiding level-shifters on the PCB. Industrial-grade -40 C to +85 C operation is essential for factory-floor enclosures. The differential analog front end rejects common-mode noise from motor drives and switching power supplies found near the imaging head.
推荐
Handheld Test and Measurement
Portable oscilloscopes, spectrum analyzers, and logic-analyzer front ends use the LTC2140IUP-14 as a dual-channel digitizer with 14-bit dynamic range. The 25 Msps rate suits audio-band and low-RF measurement, while ±1 LSB INL preserves amplitude accuracy. The LVDS DDR mode drives an FPGA deserializer at hundreds of Mbps, and the exposed pad keeps the part thermally stable inside a sealed handheld enclosure. Designers can also use one part per channel pair, scaling to 4 or 8 channels by stacking identical ICs without layout changes.
推荐
Software-Defined Radio IF Sampling
The LTC2140IUP-14 digitizes IF signals in the tens-of-MHz range, allowing digital downconversion entirely in the FPGA/DSP. Two channels sample I and Q simultaneously, eliminating the skew that would distort demodulated I/Q constellations. Per Analog Devices datasheet 21421014fa, the part supports full-rate CMOS or DDR LVDS output modes for low-EMI coupling to the digital baseband. Industrial temperature range plus the small 9x9 mm QFN footprint suit compact SDR modules used in tactical and amateur-radio equipment.
推荐
Multi-Channel Data Acquisition Systems
Modular data-acquisition systems (PCIe, PXIe, USB-DAQ) use multiple LTC2140IUP-14 ICs to scale channel count without redesign. The two simultaneously-sampling channels align perfectly across boards when fed from the same clock, and the part's industrial temperature range keeps calibration stable across a thermally mixed chassis. The 14-bit resolution suits vibration, acoustic, and strain-gauge measurements. Designers can lower cost by sharing the same PCB across 4-, 8-, and 16-channel products because each slot accepts LTC2140/41/42 interchangeably.
推荐
推荐产品汇总
工程参考数据： LTC2140IUP-14 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2141IUP-14 | LTC2142IUP-14 | LTC2140CUP-14 | LTC2140IUP-14#TRPBF |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm |
| Sample Rate (per channel) | 25 Msps | 40 Msps | 65 Msps | 25 Msps | 25 Msps |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 14 bits |
| Number of Channels | 2 | 2 | 2 | 2 | 2 |
| Operating Temperature | -40 C to +85 C (industrial) | -40 C to +85 C | -40 C to +85 C | 0 C to +70 C (commercial) | -40 C to +85 C |
| Output Interface | CMOS/DDR CMOS/DDR LVDS | CMOS/DDR CMOS/DDR LVDS | CMOS/DDR CMOS/DDR LVDS | CMOS/DDR CMOS/DDR LVDS | CMOS/DDR CMOS/DDR LVDS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
关键差异点
- Lowest-power member of pin-compatible 25/40/65 Msps family （对比 LTC2142IUP-14)
- Two simultaneously-sampling matched channels in one package （对比 LTC2174IUKG-14)
- Industrial -40 C to +85 C temperature grade standard （对比 LTC2140CUP-14)
设计说明
Solder the 64-QFN exposed pad to a continuous ground copper pour of at least 1 square inch with an array of thermal vias to an internal ground plane. At 25 Msps with LVDS outputs the part dissipates several hundred milliwatts per channel; without adequate thermal relief the junction temperature will exceed the 125 C absolute maximum in sealed enclosures. Place four to nine 0.3 mm thermal vias under the pad in a 1.2 mm pitch grid for best heat transfer.
Keep analog input traces strictly length-matched and surrounded by a solid ground pour on the top layer; route them away from LVDS/CMOS outputs to avoid digital noise coupling into the analog front end. Per Analog Devices datasheet 21421014fa, place the differential input balun or driver within 5 mm of the ADC analog input pins, and use 0402-size 0.1 uF decoupling capacitors right at every AVDD and OVDD pin with a single bulk 10 uF tantalum or ceramic on each rail.
Do not leave the exposed pad floating - it is the only ground return path for the analog core and must be soldered to ground. Do not tie OVDD to AVDD unless you are using CMOS outputs; for LVDS outputs OVDD must be 1.8 V but the analog core stays at its own rail. Finally, do not omit the input common-mode voltage; the LTC2140IUP-14 requires a defined common-mode level around mid-supply for proper sampling, even when using a fully-differential driver.
When using DDR LVDS outputs, route each LVDS pair with 100 ohm differential impedance, length-matched within 1 mm, and keep total length under 50 mm before going to the FPGA. Provide a 100 ohm termination resistor across each LVDS pair as close to the FPGA pins as possible. Series-source termination at the ADC side is generally not required because the LVDS driver is current-mode.
合规信息
Lead-free and RoHS-compliant per the '#PBF' suffix in the ordering code; not AEC-Q100 qualified (industrial grade only).
