LTC2152IUJ-12 - 12-Bit 250Msps ADC, Single 1.8V Supply, 40-QFN | Analog Devices
料号： LTC2152IUJ-12 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $68.42 | $68.42 |
| 10 | $64.18 | $641.80 |
| 100 | $58.36 | $5,836.00 |
| 500 | $55.21 | $27,605.00 |
| 1,000 | $52.04 | $52,040.00 |
LTC2152IUJ-12 概述
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog voltages at discrete instants and quantises them into binary codes; pipeline ADCs such as the LTC2152-12 use a multi-stage switched-capacitor architecture that delivers high sample rates while preserving resolution. The LTC2152-12 belongs to the category hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor, serving communications, instrumentation, and defence systems that demand wide-bandwidth, high-dynamic-range signal acquisition.
Key differentiating specifications include 12-bit resolution at 250 Msps real sampling rate, 1.8 V single supply operation, an internal high-bandwidth track-and-hold, differential analog inputs (per datasheet, the inputs must be driven differentially for specified performance), CMOS or DDR LVDS digital-output modes selectable per application, and a low-jitter clock PLL that relaxes the front-end analog filter requirements. The 40-QFN (6x6) package integrates an exposed pad that anchors the thermal and grounding strategy.
Architecture-wise, the converter uses a pipelined core with digital error correction across multiple 1.5-bit-per-stage sub-ADCs, weighted against a precision reference and reconstructed by a latency-corrected output stage; this approach delivers spurious-free dynamic range (SFDR) suitable for multi-carrier wireless basestations and pulsed radar receivers where spurious content must remain well below the wanted signal.
Typical applications include wideband digitisation of IF/RF signals in wireless infrastructure, digital oscilloscopes and spectrum analysers, radar and electronic-warfare receivers, cable-headend DOCSIS upstream capture, and medical ultrasound beamforming front-ends. The -IUJ suffix indicates the industrial temperature range (-40C to +85C) per ADI's part-numbering convention.
When designing with this part, follow ADI's recommended differential input drive network (balun or transformer-coupled op-amp), place the analog and digital 1.8 V rails on separate PCB planes with a ferrite bead between them, and expose the bottom-side thermal pad with adequate vias to a ground pour - the package lead frame cannot dissipate the converter's full-load power without this copper area.
This page synthesises ADI datasheet extracts, distributor pricing as of 2026-10-13, and a drop-in alternatives list not found on a single distributor page, giving engineers a faster cross-package/parametric path than re-querying DigiKey or Mouser manually.
直接替换替代料： LTC2152IUJ-12 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2152IUJ-12 （相同外形与封装尺寸） ——差异在于 Package, RoHS Status.
快速对比工具——选择替代料号进行并排对比：
LTC2152CUJ-12#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2151IUJ-12#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2150IUJ-12#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2152CUJ-12#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2152IUJ-12#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2152IUJ-12 最大额定值与电气特性
| 分辨率 | 12 bits |
| Sample Rate (max) | 250 Msps |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Analog Supply Voltage | 1.8 V (single supply) |
| Digital I/O Supply | 1.8 V |
| Analog Input Type | Differential (per datasheet, must be driven differentially) |
| Digital Output Modes | CMOS / DDR LVDS (selectable) |
| Operating Temperature Range (IUJ grade) | -40C to +85C (industrial) |
| 封装 | 40-QFN (UJ) 6x6 mm with exposed pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (PBF suffix) |
| SDO Pin Drive | Open-drain, ~200 ohm pull-down impedance (per datasheet) |
| Family Sibling Speeds | LTC2152-12 250 Msps / LTC2151-12 210 Msps / LTC2150-12 170 Msps |
LTC2152IUJ-12 引脚配置
| 引脚 1 | GND — Ground reference (per datasheet pinout) |
| 引脚 2 | VREF — Internal reference decoupling |
| 引脚 3 | INA+ — Differential analog input positive |
| 引脚 4 | INA- — Differential analog input negative |
| 引脚 5 | GND — Analog ground |
| 引脚 6 | OVDD — Digital output supply |
| 引脚 7 | OGND — Digital output ground |
| 引脚 8 | D11 — Data output bit 11 (MSB) |
| 引脚 9 | D10 — Data output bit 10 |
| 引脚 10 | D9 — Data output bit 9 |
| 引脚 11 | D8 — Data output bit 8 |
| 引脚 12 | D7 — Data output bit 7 |
| 引脚 13 | D6 — Data output bit 6 |
| 引脚 14 | D5 — Data output bit 5 |
| 引脚 15 | D4 — Data output bit 4 |
| 引脚 16 | D3 — Data output bit 3 |
| 引脚 17 | D2 — Data output bit 2 |
| 引脚 18 | D1 — Data output bit 1 |
| 引脚 19 | D0 — Data output bit 0 (LSB) |
| 引脚 20 | OGND — Digital output ground |
| 引脚 21 | CLKOUT+ — Differential clock output positive |
| 引脚 22 | CLKOUT- — Differential clock output negative |
| 引脚 23 | OGND — Digital output ground |
| 引脚 24 | DCO+ — Differential data clock output positive |
| 引脚 25 | DCO- — Differential data clock output negative |
| 引脚 26 | FR+ — Frame output positive |
| 引脚 27 | FR- — Frame output negative |
| 引脚 28 | OGND — Digital output ground |
| 引脚 29 | SDO — Serial data output (open-drain, needs 2k pull-up) |
| 引脚 30 | SDI — Serial data input for configuration |
| 引脚 31 | SCK — Serial configuration clock |
| 引脚 32 | CS — Chip select for serial configuration |
| 引脚 33 | OGND — Digital output ground |
| 引脚 34 | OVDD — Digital output supply |
| 引脚 35 | AVDD — Analog supply 1.8V |
| 引脚 36 | GND — Analog ground |
| 引脚 37 | CLK+ — Differential clock input positive |
| 引脚 38 | CLK- — Differential clock input negative |
| 引脚 39 | GND — Analog ground |
| 引脚 40 | AVDD — Analog supply 1.8V |
典型应用
LTC2152IUJ-12 适用于 7 应用s: Wireless Infrastructure IF Capture, Digital Oscilloscope and Spectrum Analyser Front-End, Radar and Electronic Warfare Receivers, Cable Headend DOCSIS Upstream Capture, Medical Ultrasound Beamforming, Software-Defined Radio (SDR) Wideband Digitiser, Industrial Motor Control Vibration Analysis.
Wireless Infrastructure IF Capture
The LTC2152IUJ-12's 12-bit resolution and 250 Msps real-time sample rate make it well-suited to intermediate-frequency (IF) capture in LTE and 5G NR basestation receivers. Placed after the mixer and anti-aliasing filter stage, the ADC digitises the IF band with sufficient oversampling ratio to relax analog filter selectivity and improve blocker rejection. Its differential analog inputs reject common-mode noise from the upstream RF chain, and the selectable DDR LVDS digital output streams data straight into an FPGA baseband processor at full rate without bottle-necking. The single 1.8 V supply aligns with modern radio-card power trees, reducing LDO count compared to legacy 3.3 V ADC designs.
推荐
Digital Oscilloscope and Spectrum Analyser Front-End
Wideband digital oscilloscopes and spectrum analysers use the LTC2152IUJ-12 to digitise the post-attenuator signal path with 250 Msps of real-time bandwidth per channel. Its pipelined architecture provides deterministic acquisition latency suitable for triggering and time-domain display, while the 12-bit vertical resolution exceeds traditional 8-bit scopes for small-signal measurement visibility. The differential inputs allow direct coupling from a front-end programmable-gain amplifier, eliminating the lossy balun otherwise required by single-ended ADCs in this segment. Industrial temperature grading suits portable test instruments used in field-maintenance environments.
推荐
Radar and Electronic Warfare Receivers
The LTC2152IUJ-12 suits pulsed-radar and electronic-warfare IF receiver digitisation where high spurious-free dynamic range (SFDR) is required to distinguish small targets from large clutter returns. Operating at 250 Msps, it captures a wide instantaneous bandwidth so each radar pulse yields a long time-coherent sample record, enabling high-resolution FFT processing in the downstream FPGA. Differential analog inputs reject common-mode noise from the RF front-end mixer, while selectable LVDS outputs minimise radiated emissions that could couple into sensitive microwave assemblies. The industrial temperature range supports outdoor and ground-mobile radar installations.
推荐
Cable Headend DOCSIS Upstream Capture
Cable headend equipment uses the LTC2152IUJ-12 to digitise upstream DOCSIS channels captured from the return-path spectrum, where multiple customer premise modems share the same frequency band. The 12-bit resolution preserves carrier-to-noise ratio across the densely packed upstream QAM channels, and the 250 Msps rate captures the entire DOCSIS return band in one pass without analogue channel-stacking filters. Differential inputs reject common-mode pickup from the often-noisy headend RF combiner, while selectable CMOS outputs simplify interface to lower-cost FPGAs on the headend control card. Industrial temperature rating handles the headend cabinet thermal envelope.
推荐
Medical Ultrasound Beamforming
In phased-array ultrasound systems, the LTC2152IUJ-12 digitises the post-beamformer low-IF signal per channel or in a time-multiplexed channel group. The 250 Msps sample rate provides sufficient oversampling for high-frequency transducer arrays operating above 5 MHz, while 12-bit resolution preserves B-mode dynamic range for subtle tissue differentiation. Differential analog inputs reject common-mode noise from the high-voltage transmit/receive switch matrix, and the 40-QFN compact footprint enables dense channel layout on the receiver board. The industrial temperature rating supports portable ultrasound carts and bedside imaging equipment.
推荐
Software-Defined Radio (SDR) Wideband Digitiser
Software-defined radio platforms use the LTC2152IUJ-12 to digitise the entire HF-to-L-band spectrum at once for software-tunable channel selection. With 250 Msps of real-time bandwidth, the converter covers amateur radio bands, cellular downlinks, and public-safety spectrum in a single acquisition pass, eliminating multiple narrow-band tuners. Differential analog inputs accept direct-coupled outputs from a low-noise front-end amplifier, while selectable DDR LVDS outputs deliver full-rate sample streams to a high-end FPGA running the digital down-conversion pipeline. The 40-QFN footprint suits small-form-factor SDR modules used in tactical and laboratory settings.
推荐
Industrial Motor Control Vibration Analysis
Predictive-maintenance motor-control systems use the LTC2152IUJ-12 to capture vibration sensor outputs up to ~120 MHz Nyquist bandwidth for spectral bearing-fault detection. The differential analog inputs accept IEPE-type accelerometers via a single-channel frontend, and the 12-bit resolution captures harmonics of rotating machinery with sufficient signal-to-noise for FFT-based fault signature extraction. The selectable CMOS output mode interfaces to industrial MCUs and lower-cost DSPs, while the DDR LVDS mode supports higher-end processor platforms integrating vibration analysis with closed-loop motor control. Industrial temperature rating is essential for factory-floor deployment.
推荐
推荐产品汇总
工程参考数据： LTC2152IUJ-12 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2152CUJ-12#PBF | LTC2151IUJ-12#PBF | LTC2150IUJ-12#PBF |
|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 40-QFN (UJ) 6x6 mm | 40-QFN (UJ) 6x6 mm - same | 40-QFN (UJ) 6x6 mm - same | 40-QFN (UJ) 6x6 mm - same |
| Sample Rate | 250 Msps | 250 Msps | 210 Msps | 170 Msps |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits |
| Analog Supply | 1.8 V single | 1.8 V single | 1.8 V single | 1.8 V single |
| Temperature Range | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Digital Output | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS | CMOS / DDR LVDS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined |
| Relative Cost (1ku ref) | $58.36 (list) | Lower (commercial grade) | Lower (slower speed) | Lowest of family |
关键差异点
- Highest sample rate in the LTC215x-12 family （对比 LTC2151IUJ-12#PBF)
- Industrial temperature grade coverage （对比 LTC2152CUJ-12#PBF)
- Same-die pin-compatibility across speed grades （对比 LTC2150IUJ-12#PBF)
设计说明
Driving the analog input single-ended is the most common LTC2152-12 design mistake. Per the LTC2152-12 datasheet, both INA+ and INA- must be driven differentially for the SNR and SFDR curves to hold. Use a balun or a fully-differential amplifier (e.g., AD8138 or ADA4930 family) with centre-tap tied to a clean analog common-mode voltage, typically derived from the LTC2152-12 VCM output pin. A single-ended drive typically costs 6-10 dB of SNR and elevates even-order harmonics.
Keep the analog (AVDD) and digital (OVDD) supplies on separate PCB planes that meet only at the converter's GND paddle. Place 0.1 uF X7R ceramic decoupling caps as close as possible to every AVDD and OVDD pin and a single 10 uF bulk capacitor per plane. Route the differential CLK+/CLK- pair first to minimise jitter; reference the LVDS outputs to a 100 ohm differential trace kept well away from the analog input traces. Tie the bottom-exposed thermal pad to the analog ground plane with at least nine thermal vias for heat spreading.
Place a ferrite bead between AVDD and OVDD 1.8 V rails to prevent digital switching noise from coupling into the analog front-end. The estimated AVDD current at 250 Msps with CMOS outputs is in the 100-150 mA range; OVDD current is comparable. Choose ferrite beads with low DC resistance to avoid excessive dropout at full CMOS toggle rate. Estimated: with 1.8 V supply and 120 mA AVDD + 130 mA OVDD, the total converter power dissipation is approximately 450 mW at 250 Msps.
Jitter in the CLK+/CLK- pair directly converts to aperture-jitter-limited SNR. Use a low-jitter clock source such as a differential crystal oscillator or the ADI AD9516 family of clock generators; per the LTC2152-12 datasheet SNR figures assume < 200 fs RMS clock jitter. Keep CLK+/CLK- traces length-matched to within 1 mm and 50 ohm single-ended-controlled-impedance. Skew between the two differential traces will inject common-mode noise into the ADC clock input.
合规信息
RoHS and lead-free status confirmed by #PBF suffix in the orderable part number per ADI datasheet convention. AEC-Q100 qualification does not apply; this part is not automotive qualified.
