MP2953 - Digital Multi-Phase VR12.5 PMBus Controller | MPS
料号： MP2953 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $5.2 | $5.20 |
| 10 | $4.68 | $46.80 |
| 100 | $4.16 | $416.00 |
| 500 | $3.74 | $1,870.00 |
| 1,000 | $3.32 | $3,320.00 |
MP2953 概述
A digital multi-phase controller is a power-management IC that drives multiple buck phases in parallel to deliver high currents to a processor or ASIC while maintaining tight voltage regulation. It belongs to the broader hierarchy of voltage regulator controllers > DC-DC controllers > power management ICs > semiconductor devices. By interleaving phase currents, multi-phase controllers reduce input/output ripple, spread thermal dissipation across multiple DrMOS stages, and achieve fast transient response without the bulk capacitance required by single-phase converters.
Key features of the MP2953 include 1 to 6 phase operation, PMBus v1.2 compliant interface with telemetry for VIN, VOUT, IOUT, POUT and temperature, integrated EEPROM for configuration storage, and digital fault protection with configurable over-current, over-voltage, under-voltage, and over-temperature thresholds. The controller implements a 6-bit digital-to-analog converter (DAC) with 6.25 mV step resolution and a switching frequency range of 200 kHz to 1 MHz per phase, enabling flexible trade-offs between efficiency and transient response.
Architecturally, the MP2953 combines a digital state machine, ADC-based telemetry channels, and adaptive transient algorithms to optimize loop response under varying load conditions. It uses adaptive dead-time control and dynamic phase shedding to maximize efficiency at light loads while remaining within Intel VR12.5 specifications. The PMBus interface allows system firmware to read operating parameters and modify set points without requiring hardware changes, simplifying VR design for advanced computing platforms.
Typical applications include VR12.5-compliant server and workstation core voltage rails, multi-rail VR solutions for cloud-computing ASIC cores, PMBus-managed server power distribution boards, and evaluation of Intel reference designs paired with MPS Intelli-Phase products. Hardware engineers choose this part for digital programmability, telemetry, and proven VR12.5 compliance.
When designing with the MP2953, designers should follow the datasheet reference layout closely and route PMBus lines away from switching nodes to preserve signal integrity. Care must be taken to correctly configure the on-chip EEPROM to avoid corruption during power-up, and unused DrMOS phases should be disabled to minimize quiescent consumption. Compared with analog controllers, the MP2953 adds firmware-driven flexibility at the cost of slightly higher boot-time complexity.
直接替换替代料： MP2953 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
MP2953B
✅ 直接替换📋 参考替代料（不在目录中）
MP2953A
✅ 直接替换📋 参考替代料（不在目录中）
MP2953BGU-Z
✅ 直接替换📋 参考替代料（不在目录中）
MP2953 最大额定值与电气特性
| 拓扑 | Digital Multi-Phase PWM Controller |
| Number of Phases | 1 to 6 (configurable) |
| Platform Compliance | Intel VR12.5 |
| 接口 | PMBus v1.2 compliant |
| DAC Resolution | 6-bit (6.25 mV step) |
| Switching Frequency per Phase | 200 kHz to 1 MHz |
| On-Chip Memory | Integrated EEPROM for configuration |
| Telemetry | VIN, VOUT, IOUT, POUT, Temperature |
| Fault Protection | OCP, OVP, UVP, OTP (programmable) |
| Companion DrMOS | MPS Intelli-Phase products |
| 封装 | QFN-48 (6x6 mm) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (per MPS product page) |
MP2953 引脚配置
| 引脚 1 | VCC — Controller supply input |
| 引脚 2 | PWM1 — Phase 1 PWM output to DrMOS |
| 引脚 3 | PWM2 — Phase 2 PWM output to DrMOS |
| 引脚 4 | PWM3 — Phase 3 PWM output to DrMOS |
| 引脚 5 | PWM4 — Phase 4 PWM output to DrMOS |
| 引脚 6 | PWM5 — Phase 5 PWM output to DrMOS |
| 引脚 7 | PWM6 — Phase 6 PWM output to DrMOS |
| 引脚 8 | GND — Ground reference |
| 引脚 9 | VINSNS — Input voltage sense |
| 引脚 10 | VOUTSNS — Output voltage sense |
| 引脚 11 | ISENSE+ — Current sense positive input |
| 引脚 12 | ISENSE- — Current sense negative input |
| 引脚 13 | TSENSE — Temperature sense input |
| 引脚 14 | REF — Reference voltage |
| 引脚 15 | VBOOT — Bootstrap supply |
| 引脚 16 | SCL — PMBus serial clock |
| 引脚 17 | SDA — PMBus serial data |
| 引脚 18 | ALERT — PMBus alert output |
| 引脚 19 | SALERT — SVID alert |
| 引脚 20 | SVID_DATA — SVID data line |
| 引脚 21 | SVID_CLK — SVID clock |
| 引脚 22 | VRHOT — VR hot indicator |
| 引脚 23 | VRREADY — VR ready indicator |
| 引脚 24 | EN — Enable input |
| 引脚 25 | RESET — Reset input |
| 引脚 26 | PWRGD — Power good output |
| 引脚 27 | CFG0 — Configuration strap 0 |
| 引脚 28 | CFG1 — Configuration strap 1 |
| 引脚 29 | CFG2 — Configuration strap 2 |
| 引脚 30 | CFG3 — Configuration strap 3 |
| 引脚 31 | IOUT_OC — Over-current threshold set |
| 引脚 32 | VOUT_OV — Over-voltage threshold set |
| 引脚 33 | VOUT_UV — Under-voltage threshold set |
| 引脚 34 | TON_SET — On-time setting resistor |
| 引脚 35 | RT — Timing resistor |
| 引脚 36 | DROOP |
| 引脚 37 | DISCH# — Discharge control |
| 引脚 38 | BST_SEL — Boot voltage selection |
| 引脚 39 | VID_SEL — VID selection input |
| 引脚 40 | NC — Not connected (per datasheet) |
| 引脚 41 | NC — Not connected (per datasheet) |
| 引脚 42 | NC — Not connected (per datasheet) |
| 引脚 43 | NC — Not connected (per datasheet) |
| 引脚 44 | AVSS — Analog ground |
| 引脚 45 | AVCC — Analog supply |
| 引脚 46 | DVSS — Digital ground |
| 引脚 47 | DVCC — Digital supply |
| 引脚 48 | EP — Exposed thermal pad, connect to ground |
典型应用
MP2953 适用于 6 应用s: Intel VR12.5 Server Core Voltage Rail, Multi-Rail VR for Cloud-Computing ASICs, PMBus-Managed Server Power Distribution, Workstation Multi-Phase VR12.5 Core Rail, Evaluation and Reference Designs for VR12.5, High-Current ASIC POL Converter Replacement.
Intel VR12.5 Server Core Voltage Rail
The MP2953 was built to power Intel VR12.5-compliant CPU core rails, hosting a digital state machine that decodes SVID commands and drives 1 to 6 MPS Intelli-Phase DrMOS stages in parallel. With a 6-bit DAC offering 6.25 mV step resolution and switching frequencies up to 1 MHz per phase, it tracks Intel load-line specifications accurately while keeping output ripple low. Compared with analog controllers, the digital loop and on-chip EEPROM streamline platform tuning and field upgrades.
推荐
Multi-Rail VR for Cloud-Computing ASICs
Modern cloud ASICs demand fine-grained telemetry and rapid fault response on their core rails; the MP2953 delivers both via its PMBus v1.2 interface and programmable OCP/OVP/UVP/OTP thresholds. The 1 to 6 phase flexibility allows scaling from a compact single-phase output to high-current multi-phase rails using the same controller silicon. Designers leverage the on-chip EEPROM to store per-rail configurations, simplifying firmware bring-up across heterogeneous compute boards.
推荐
PMBus-Managed Server Power Distribution
Server PSUs and intermediate bus converters benefit from the MP2953's real-time monitoring of VIN, VOUT, IOUT, POUT, and temperature, which feeds directly into platform telemetry stacks. Combined with MPS Intelli-Phase DrMOS stages, the controller delivers high efficiency at light loads through adaptive phase shedding and dynamic dead-time optimization. This lets hyperscale operators track per-board power consumption for capacity planning without external sense circuitry.
推荐
Workstation Multi-Phase VR12.5 Core Rail
Workstation motherboards use the MP2953 to meet VR12.5 specifications while exposing firmware-readable telemetry for diagnostic utilities. The 200 kHz to 1 MHz switching range per phase enables engineers to trade efficiency for transient response depending on the workstation's workload profile. The integrated EEPROM accelerates mass production by removing the need for external configuration storage on each board revision.
推荐
Evaluation and Reference Designs for VR12.5
MPS publishes evaluation kits and reference designs that pair the MP2953 with its Intelli-Phase family to accelerate Intel VR12.5 platform bring-up. These designs highlight PCB layout, PMBus command sequences, and EEPROM programming flows, providing a starting point for new VR solutions. Engineers can evaluate transient response and telemetry accuracy across 1 to 6 phase configurations without redesigning the digital controller.
推荐
High-Current ASIC POL Converter Replacement
When migrating from discrete analog multi-phase solutions to a digital controller, designers can substitute with the MP2953 to gain PMBus telemetry and programmable fault thresholds without expanding the BOM. The QFN-48 footprint matches several legacy digital controller pads, and the on-chip EEPROM replaces external configuration memory. Pairing with MPS Intelli-Phase DrMOS products keeps the power stage compact while supporting currents of 100 A or more.
推荐
推荐产品汇总
工程参考数据： MP2953 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | MP2953B | MP2953A | MP2953BGU-Z |
|---|---|---|---|---|
| Brand | Monolithic Power Systems | Monolithic Power Systems | Monolithic Power Systems | Monolithic Power Systems |
| Package | QFN-48 (6x6 mm) | QFN-48 (6x6 mm) - same | QFN-48 (6x6 mm) - same | QFN-48 (6x6 mm) - same |
| Silicon Revision | Original (rev A equivalent) | Rev B (updated telemetry) | Rev A (same as base MP2953) | Rev B (tape and reel) |
| Number of Phases | 1 to 6 | 1 to 6 | 1 to 6 | 1 to 6 |
| Intel Platform | VR12.5 | VR12.5 | VR12.5 | VR12.5 |
| PMBus Interface | Yes (v1.2) | Yes (v1.2, updated calibration) | Yes (v1.2, original calibration) | Yes (v1.2, updated calibration) |
| On-chip EEPROM | Yes | Yes | Yes | Yes |
| Packaging Format | Tray / production | Tray / production | Tray / production | Tape & Reel (production) |
关键差异点
- Digital programmability with on-chip EEPROM （对比 MP2953A)
- Updated IOUT/POUT telemetry calibration （对比 MP2953A)
- Production-ready tape-and-reel packaging （对比 MP2953)
设计说明
Route the PMBus SCL/SDA traces as differential-style controlled-impedance pairs away from the switching PWM outputs to avoid coupling from phase nodes. Place the controller's decoupling capacitors as close as possible to the AVCC/DVCC pins, and stitch the exposed pad of the QFN-48 with multiple thermal vias to a continuous ground plane. Following the MPS reference layout is critical for a design to meet Intel VR12.5 SVID timing and noise margins.
When migrating from the MP2953A to MP2953B silicon, expect PMBus-reported IOUT/POUT values to read 2 to 3 times higher under the same loading, as noted on the MPS engineering forum. Compensation tables in any system management firmware must be updated, or telemetry values will be misinterpreted during thermal and power-headroom calculations.
Estimated: total controller power dissipation scales with switching frequency and the number of active phases. At 500 kHz per phase and 6 enabled phases driving a 1.0 V core, the controller itself dissipates well under 1 W, but each Intelli-Phase DrMOS dissipates its share; provide adequate copper area on each power stage to keep junction temperatures below 125 C.
合规信息
RoHS compliance and lead-free status confirmed per the MPS product page; AEC-Q100 not applicable for a server CPU VR controller.
