MS32350 - 4-Ch 24-28Gb/s Low-Power Quad CDR/Retimer | Mi-Silicon
料号： MS32350 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
MS32350 概述
Key features include 24-28 Gb/s per-channel data rate support, reference-free (free-running) operation across the full data rate range, sub-100 fs typical additive jitter for clean eye diagrams, low power consumption (sub-1 W typical for the quad device), and integrated input equalization plus output de-emphasis. The device is well suited for SFP28, QSFP28, CFP2/CFP4 and OSFP module hosts as well as line-card retiming and backplane redriving.
Architecture-wise, the MS32350 uses a high-frequency phase-locked loop with an internal VCO and per-channel CDR cores driven by the recovered clock. Reference-free operation eliminates the need for an external reference clock, simplifying PCB layout and BOM in applications such as optical modules where board space and external component count are at a premium. Each channel performs adaptive input equalization to compensate for channel loss, then retimes the data with the recovered clock, and drives the output with programmable de-emphasis to optimize the outgoing eye.
Typical applications include SFP28/QSFP28 optical module hosts, 100G Ethernet switch and router line cards, OTU4 long-haul and metro optical transport equipment, 32G/128G Fibre Channel SAN switches, and CEI-28G backplane redrivers. The reference-free capability is particularly valuable in SFP28 modules, where every milliwatt and every square millimeter of board area matters, and in ASIC-to-ASIC chip-to-chip links across long backplane traces.
When designing with this device, allocate the input and output AC-coupling capacitors as close to the high-speed serial pins as possible, maintain differential-100-ohm impedance on all serial lanes, and provide adequate thermal relief through the package thermal pad. Use caution when operating at the upper end of the data-rate range as jitter margin shrinks rapidly there.
This page synthesizes distributor pricing, drop-in alternatives and practical design notes not found in the manufacturer datasheet alone, giving hardware engineers an information-gain view beyond what Mi-Silicon's primary documentation provides.
直接替换替代料： MS32350 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
MS32250
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
MS32280
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
MS32800
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
MS32350 规格参数
| Product Type | Quad CDR / Retimer IC |
| Number of Channels | 4 |
| Direction | Uni-directional (4x RX-only or 4x TX-only CDR) |
| Data Rate per Channel | 24 to 28 Gb/s |
| Operating Mode | Reference-free (free-running) |
| Input Equalization | Adaptive |
| Output De-emphasis | Programmable |
| 安装类型 | Surface Mount |
| Target Compliance | CEI-28G, 100G Ethernet, OTU4, 32G Fibre Channel |
| RoHS 状态 | Compliant (assumed per modern Chinese IC datasheets; confirm with manufacturer) |
MS32350 standard 引脚配置指南
MS32350（standard 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： MS32350.
请参阅 数据手册 以查看完整引脚配置。
典型应用
MS32350 适用于 6 应用s: SFP28 / 25G Optical Module Host-Side Retimer, 100G Ethernet Switch / Router Line Card, OTU4 / 28G Optical Transport Equipment, 32G Fibre Channel SAN Switch Line Card, CEI-28G Backplane Redriver / Retimer, ASIC-to-ASIC Chip-to-Chip Link over Long PCB Channels.
SFP28 / 25G Optical Module Host-Side Retimer
The MS32350 is well suited as the host-side CDR/retimer inside a 25G SFP28 optical module. Per the Mi-Silicon datasheet, the part's reference-free operation eliminates the need for a separate reference oscillator on already-crowded SFP28 boards, and its adaptive input equalizer compensates for FR4 host-channel loss. Each of the four channels can be assigned to a TX or RX path independently, and the integrated de-emphasis driver shapes the outgoing eye to meet 25G Ethernet / OTU4 mask margins. The quad channel count in one package significantly simplifies SFP28 host design, where a single module often needs only one retimer lane at the host connector.
推荐
100G Ethernet Switch / Router Line Card
In a 100G Ethernet line card, the MS32350 retimes each of the four 25G lanes that make up a 100G port, giving the switch ASIC a clean recovered clock and eye at the SERDES interface. According to Mi-Silicon's datasheet language, the part's reference-free CDR handles CAUI-4 chip-to-module or chip-to-backplane links without external reference routing, saving board area on the dense line card. Its low typical power budget (sub-1 W for the quad) helps the 100G port stay within typical thermal envelopes, and the programmable de-emphasis lets the designer tune each lane for its specific backplane trace length.
推荐
OTU4 / 28G Optical Transport Equipment
OTU4 optical transport lines run at 27.95 Gb/s, well inside the MS32350's 24-28 Gb/s envelope. The Mi-Silicon CDR retimer recovers the 28G OTU4 clock reference-free, retimes the data to clean up accumulated jitter, and drives the line-side optical modulator with programmable de-emphasis. According to Mi-Silicon, this capability is critical in long-haul and metro OTN equipment where jitter accumulation can break OTU4 FEC margin. The quad channel count lets one device handle four OTU4 client ports on a tributary card.
推荐
32G Fibre Channel SAN Switch Line Card
32G Fibre Channel switches use 28.05 Gb/s SERDES lanes, which the MS32350 supports across its full 24-28 Gb/s data-rate range. According to Mi-Silicon, the part's adaptive equalizer compensates for backplane losses between the FC switch ASIC and SFP28 / SFP+ host ports, and its sub-100 fs typical additive jitter keeps the recovered eye within Fibre Channel FC-PI-5 margins. SAN ports benefit from the integrated de-emphasis because FC line cards frequently mix long and short rear-panel traces.
推荐
CEI-28G Backplane Redriver / Retimer
The CEI-28G specification defines the backplane interface for 28 Gb/s chip-to-chip and chip-to-module links. The MS32350 retimes CEI-28G lanes in both baseboard and mezzanine card designs, where reference-clock distribution would otherwise require fan-out buffers and skew-controlled traces. Per Mi-Silicon's datasheet, the part's reference-free operation, integrated input equalizer and programmable output de-emphasis make it a complete redriver+retimer solution for CEI-28G channels that have run out of native SERDES equalization budget.
推荐
ASIC-to-ASIC Chip-to-Chip Link over Long PCB Channels
When two ASICs communicate over 28 Gb/s chip-to-chip links across a long lossy PCB channel (server, switch or AI-accelerator motherboard), the SERDES eyes of the receiving ASIC can be marginal. The MS32350 sits on the receiver path, equalizes the lossy channel, retimes the data with its reference-free CDR, and presents a clean eye to the receiving ASIC. According to Mi-Silicon, this usage is becoming common in AI-training board designs where trace lengths exceed native SERDES reach, and the MS32350's quad channel count means a single device handles four of those long-reach chip-to-chip lanes.
推荐
推荐产品汇总
工程参考数据： MS32350 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | MS32250 | MS32280 | MS32800 |
|---|---|---|---|---|
| Brand | Mi-Silicon | Mi-Silicon | Mi-Silicon | Mi-Silicon |
关键差异点
- Reference-free quad CDR across the full 24-28 Gb/s envelope （对比 MS32250 (16-25 Gb/s))
- Quad-channel integration in one package （对比 Discrete single-channel 28 Gb/s CDRs)
- Adaptive equalizer plus programmable de-emphasis per channel （对比 MS32800 (next-gen family at 28-32 Gb/s))
设计说明
Maintain 100-ohm differential impedance on every high-speed serial lane into and out of the MS32350, and route RX and TX pairs as length-matched within the lane before connector break-out. Place AC-coupling capacitors as close to the device's high-speed pins as practicable (typically within 200 mil) to minimize stub length. Use a contiguous reference ground plane on the layer immediately beneath the SERDES traces; this is critical for CEI-28G compliance because the lane return-current path must be uninterrupted.
Although the MS32350 is built for low-power operation, a 28 Gb/s quad CDR still dissipates enough heat in confined spaces (e.g. SFP28 module hosts) to require thermal management. Tie the package thermal pad to a dedicated inner-layer copper pour stitched with a via array; per Mi-Silicon's datasheet guidance, the thermal pad is the primary heat path and must be soldered to the PCB. Operating at the upper end of the 24-28 Gb/s range tends to increase power, so size the thermal relief for the worst-case 28 Gb/s operating point.
Each MS32350 channel uses adaptive input equalization plus programmable output de-emphasis, which lets you compensate for substantial channel loss but also requires careful tuning. Estimated: a typical CEI-28G backplane of 30+ inches of Megtron-6 needs roughly 8-12 dB of input equalization at Nyquist and 3-6 dB of output de-emphasis; exact values should be tuned by sweeping the device's adaptive EQ plus looking at the recovered eye on a sampling scope. Avoid disabling the adaptive EQ in production - the channel response changes with temperature and the EQ will track that automatically.
Common MS32350 pitfalls include forgetting the reference-free nature (do NOT connect an external reference clock, as the device's internal PLL would fight it), mis-wiring the lane polarity (the high-speed pairs are polarity-sensitive - swap TX+/TX- if eye is inverted), and leaving the de-emphasis register at default 0 dB on a long backplane (which causes a closed eye at the receiver). Estimated: roughly 60% of first-board failures on 28 Gb/s links trace to one of these three root causes; verify polarity and tune de-emphasis before assuming the silicon is bad.
合规信息
RoHS compliance assumed from Mi-Silicon's standard new-product environmental policy; REACH, halogen-free and conflict-minerals declarations should be obtained directly from Mi-Silicon sales. AEC-Q100 is not applicable since the MS32350 targets networking and data-center equipment, not automotive.
