PCA9548A - 8-Channel I2C Switch with Reset | TI
料号： PCA9548A ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $1.62 | $1.62 |
| 10 | $1.45 | $14.50 |
| 100 | $1.18 | $118.00 |
| 500 | $0.98 | $490.00 |
| 1,000 | $0.79 | $790.00 |
PCA9548A 概述
An I2C bus switch (also called an I2C multiplexer or bus expander) is an interface IC that fans a single upstream SCL/SDA pair out to multiple downstream bus segments. In the system hierarchy it sits between the host controller and peripheral devices, letting one controller manage many more slaves than the address space would otherwise allow, and isolating bus segments to resolve address conflicts or capacitive-loading limits.
Key features include the eight selectable downstream SCx/SDx channel pairs, voltage translation capability (any low-voltage section can be interfaced with any high-voltage section when the switch pass-gate voltage is set at or below the lowest bus voltage), a reset input that recovers from bus lockup by power-cycling the selected channel through an internal power-on-reset circuit, and support for both 100 kHz and 400 kHz bus speeds.
Technically, the PCA9548A uses pass-gate transistor switches between the upstream and downstream pairs. Three hardware address pins (A0, A1, A2) allow up to eight PCA9548A devices to share the same I2C bus, expanding one controller port to as many as 64 separate bus segments. The pass-gate design means channel on-resistance and gate drive define the translation window, and channels can be enabled individually or in any combination per the control register.
Typical applications include buffering level-shifted I2C segments in servers and networking equipment, resolving address conflicts between identical sensors on one controller, isolating capacitive loads in long backplanes, and automotive or industrial control buses where a resettable switch simplifies fault recovery.
When designing with this part, ensure the pass-gate switch voltage is referenced to the lowest downstream bus voltage so the translation function holds the correct logic levels; the RESET pin should be driven from a supervisor or GPIO to recover hung buses.
This page synthesizes distributor pricing, drop-in alternatives including the pin-compatible TCA9548A, and practical design notes beyond what the manufacturer datasheet provides.
直接替换替代料： PCA9548A ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： PCA9548A （相同外形与封装尺寸） ——差异在于 Number of Channels, Reset Input, Supply Voltage Range.
快速对比工具——选择替代料号进行并排对比：
TCA9548APWR
✅ 直接替换✓ 有现货
$1.82 / 个
查看数据手册 →PCA9548APW
✅ 直接替换📋 参考替代料（不在目录中）
PCA9548A 最大额定值与电气特性
| 功能 | 8-channel bidirectional I2C translating switch |
| Number of Channels | 8 downstream SCx/SDx pairs |
| Supply Voltage Range | 2.3 V to 5.5 V |
| I2C Bus Speed Support | Standard-Mode 100 kHz, Fast-Mode 400 kHz |
| Control Interface | I2C/SMBus, single 8-bit control register |
| Hardware Address Pins | 3 (A0, A1, A2) - up to 8 devices per bus |
| Reset Input | Yes, active-low RESET |
| Voltage Translation | Yes, via pass-gate switch voltage referencing |
| 封装 | 24-TSSOP (PW) |
| 安装类型 | Surface Mount |
| 接口类型 | 2-wire bus (SCL/SDA) |
| Channel Selection | Individual or any combination of channels |
| Power-On Reset | Internal, resets registers to default state |
| RoHS 状态 | Compliant |
PCA9548A 引脚配置
| 引脚 1 | A0 — Hardware address input 0 |
| 引脚 2 | A1 — Hardware address input 1 |
| 引脚 3 | RESET — Active-low reset input; power-cycles selected channel(s) |
| 引脚 4 | GND — Ground |
| 引脚 5 | SD0 — Serial data, channel 0 |
| 引脚 6 | SC0 — Serial clock, channel 0 |
| 引脚 7 | SD1 — Serial data, channel 1 |
| 引脚 8 | SC1 — Serial clock, channel 1 |
| 引脚 9 | SD2 — Serial data, channel 2 |
| 引脚 10 | SC2 — Serial clock, channel 2 |
| 引脚 11 | SD3 — Serial data, channel 3 |
| 引脚 12 | SC3 — Serial clock, channel 3 |
| 引脚 13 | SD4 — Serial data, channel 4 |
| 引脚 14 | SC4 — Serial clock, channel 4 |
| 引脚 15 | SD5 — Serial data, channel 5 |
| 引脚 16 | SC5 — Serial clock, channel 5 |
| 引脚 17 | SD6 — Serial data, channel 6 |
| 引脚 18 | SC6 — Serial clock, channel 6 |
| 引脚 19 | SD7 — Serial data, channel 7 |
| 引脚 20 | SC7 — Serial clock, channel 7 |
| 引脚 21 | A2 — Hardware address input 2 |
| 引脚 22 | SCL — Upstream serial clock |
| 引脚 23 | SDA — Upstream serial data |
| 引脚 24 | VCC — Supply voltage, 2.3 V to 5.5 V |
典型应用
PCA9548A 适用于 6 应用s: Server and Backplane I2C Management, I2C Address Conflict Resolution, Voltage-Level Translation Between Mixed Rails, Industrial Control and PLC Systems, Automotive Body and Infotainment Networks, Test and Measurement Instrumentation.
Server and Backplane I2C Management
Servers, storage shelves, and telecom backplanes fan a single BMC I2C port out to dozens of power supplies, fan controllers, and temperature sensors. The PCA9548A's eight downstream segments and three address pins (up to eight devices per bus, 64 segments total) let one controller isolate each shelf or FRU onto its own bus, containing faults and reducing bus capacitance. Operating from 2.3 V to 5.5 V with 400 kHz Fast-Mode support, it keeps polling cycles short across long backplane traces, while the RESET pin gives the BMC a hardware path to recover a segment that hangs - critical for systems requiring high availability without service interruption.
推荐
I2C Address Conflict Resolution
Many popular I2C sensors, EEPROMs, and RTCs ship with fixed or narrowly configurable addresses. Placing identical devices behind different PCA9548A channels lets one controller talk to multiple same-address parts by enabling only one channel at a time via the 8-bit control register. Because the switch is a passive bidirectional pass gate, no protocol translation or timing penalty is introduced at 100 kHz or 400 kHz. Designers simply write the channel-select byte before accessing the target device, a pattern supported by common Linux (i2c-mux) and MCU drivers, making this the lowest-effort fix for duplicate-address designs in consumer and industrial hardware.
推荐
Voltage-Level Translation Between Mixed Rails
Designs mixing 5 V microcontrollers with 1.8 V or 3.3 V sensor islands can use the PCA9548A's pass-gate translation characteristic: per the NXP datasheet, setting the switch voltage at or below the lowest bus voltage lets the device safely bridge dissimilar rails. The upstream pair connects to the higher-voltage controller while selected downstream segments operate at the peripheral rail. This eliminates separate level-shifter ICs on each bus segment and reduces BOM count. The device's 2.3 V to 5.5 V core supply supports the common 3.3 V and 5 V controller domains directly, and 400 kHz throughput is preserved across the translation boundary.
推荐
Industrial Control and PLC Systems
In programmable logic controllers and factory automation racks, the PCA9548A segments I2C buses between a main controller and plug-in I/O modules, current monitors, and configuration EEPROMs. Channel isolation means a shorted or misbehaving module cannot drag down the shared bus, and the active-low RESET input driven from a supervisor recovers a hung segment automatically. The 2.3 V to 5.5 V supply range suits both legacy 5 V backplanes and modern 3.3 V logic. Fast-Mode 400 kHz support shortens scan cycles across eight modules, improving control-loop latency while keeping wiring to a simple two-wire bus throughout the cabinet.
推荐
Automotive Body and Infotainment Networks
Automotive ECU clusters use the PCA9548A (with Q100-grade sourcing practices) to branch a central I2C bus to ambient-light controllers, touch sensors, and audio codec sub-boards. Its active-low RESET enables fault-tolerant recovery after load-dump transients or ESD events corrupt a downstream bus state, and channel isolation keeps a stuck slave on one door module from blocking the rest of the network. The wide 2.3 V to 5.5 V supply tolerates battery-rail regulation variance, and 400 kHz operation supports fast scanning of keypads and lighting controllers during wake-up sequences without exceeding two-wire harness budgets.
推荐
Test and Measurement Instrumentation
Bench instruments and modular test frames route I2C from a main controller to front-end attenuators, calibration EEPROMs, and display drivers using the PCA9548A. Eight independently switchable segments let the firmware service many boards with a single connector, and the hardware address pins permit cascading additional switches for even larger frames. Because the pass-gate switch is transparent to protocol timing, instruments can run calibration sequences at 400 kHz without timing artifacts. The RESET pin doubles as a safety interlock: firmware can isolate all analog front-end buses during mode changes, guaranteeing a clean bus state before re-enabling channels.
推荐
推荐产品汇总
工程参考数据： PCA9548A ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | TCA9548APWR | PCA9548APW |
|---|---|---|---|
| Package | 24-TSSOP | 24-TSSOP - same | 24-TSSOP - same |
| Brand | Texas Instruments | Texas Instruments | NXP Semiconductors |
| Number of Channels | 8 | 8 | 8 |
| Supply Voltage Range | 2.3 V to 5.5 V | 1.65 V to 5.5 V | 2.3 V to 5.5 V |
| Bus Speed | 100 kHz / 400 kHz | 100 kHz / 400 kHz | 100 kHz / 400 kHz |
| Reset Input | Yes (active-low) | Yes (active-low, reset errata corrected) | Yes (active-low) |
| Hardware Address Pins | 3 (A0-A2) | 3 (A0-A2) | 3 (A0-A2) |
| Voltage Translation | Yes (pass-gate) | Yes (pass-gate) | Yes (pass-gate) |
关键差异点
- Eight channels with combination selection （对比 PCA9546A)
- Extended low-voltage operation in successor （对比 TCA9548APWR)
- Reset-based bus recovery （对比 NXP PCA9548APW)
设计说明
TI acknowledges a reset errata on the PCA9548A (the reset function may not restore all registers correctly under specific conditions) which was corrected in the TCA9548A. If your design relies on RESET for fault recovery, either validate the fix in your firmware or select TCA9548APWR, which is pin-to-pin identical and corrects the errata per TI E2E support. This is the single most cited reason TI recommends the TCA9548A for new designs.
The channel switch is a passive pass-gate, so each enabled channel adds series resistance into the bus. At 400 kHz Fast-Mode with several channels enabled simultaneously, budget the pass-gate resistance into the pull-up resistor calculation: total bus capacitance times required rise time determines the minimum pull-up strength. Keeping the switch voltage at or below the lowest bus segment voltage ensures proper translation logic levels per the NXP datasheet.
Place 0.1 uF decoupling close to the VCC pin (pin 24) with a solid ground return via near pin 4. Route the upstream SCL/SDA traces short and direct; downstream channel pairs may be routed as a group per bus segment. Tie the RESET pin to a host GPIO or supervisor output with a pull-up to VCC - never leave it floating, or spurious resets can disable channels mid-transaction.
合规信息
RoHS compliant and lead-free per TI product listing. REACH, halogen-free, and conflict-minerals status not stated in provided data - verify on TI.com quality pages.
