PIC24HJ128GP306AT-I/PT - 40 MIPS 128KB Flash 16-bit MCU | Microchip
料号： PIC24HJ128GP306AT-I/PT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.86 | $8.86 |
| 10 | $7.81 | $78.10 |
| 100 | $6.52 | $652.00 |
| 500 | $5.74 | $2,870.00 |
| 1,000 | $5.1 | $5,100.00 |
| 3,000 | $4.61 | $13,830.00 |
PIC24HJ128GP306AT-I/PT 概述
A 16-bit microcontroller (MCU) is an integrated processor that fetches, decodes and executes 16-bit-wide instructions in a single cycle, offering higher code density, faster arithmetic and richer peripherals than 8-bit MCUs while remaining simpler and lower-power than 32-bit ARM Cortex-M parts. The PIC24H family sits in Microchip's 16-bit MCU portfolio between the PIC24F low-power line and the dsPIC33F DSP-enabled family, supporting seamless migration paths and pin compatibility with dsPIC30F devices.
Key features of the PIC24HJ128GP306AT-I/PT include a 16-bit modified Harvard CPU core with single-cycle 16x16 MAC, dual 40 MHz oscillator pins with PLL (FOSC up to 80 MHz / 40 MIPS), 53 general-purpose I/O lines, two UART/USART modules, two SPI interfaces, two I2C buses, an IrDA/LINbus-capable UART, two CAN 2.0b controllers, an 8-channel 10/12-bit ADC, four 16-bit timers, and a 16-bit Parallel Master Port (PMP) for external memory or graphics interfaces.
The architecture is based on a modified Harvard bus with separate 24-bit instruction and 16-bit data paths, an 8-deep hardware stack and 17x17-bit multiplier with DSP extensions, while the IC uses a low-power CMOS process supporting 3.0V to 3.6V VDD operation. Five low-power modes (Idle, Doze, Sleep, Deep Sleep and alternate clock switchover) make it suited for battery-aware designs.
Typical applications include industrial motor control, sensor signal conditioning, CAN-bus node controllers, LIN master/slave nodes, building automation, graphical user interfaces, and portable instrumentation. The 64-pin TQFP and PMP peripheral also enable small TFT-LCD HMI systems.
Designers should verify minimum and maximum VDD (3.0V to 3.6V), use 0.1 uF + 10 uF decoupling per VDD/AVDD pair, and follow the I/O source/sink current limits from the datasheet. The MPLAB X IDE plus XC16 compiler and the MPLAB ICD programmer/debugger cover firmware development and in-circuit debug.
This page consolidates distributor pricing, pin-compatible same-family alternatives, and PCB-level design guidance not found in the standalone manufacturer datasheet, helping engineers select the right PIC24H variant faster.
直接替换替代料： PIC24HJ128GP306AT-I/PT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： PIC24HJ128GP306AT-I/PT （相同外形与封装尺寸） ——差异在于 Package, ADC, Timers, Program Memory (Flash), Maximum CPU Speed.
快速对比工具——选择替代料号进行并排对比：
PIC24HJ128GP306A-I/PT
✅ 直接替换📋 参考替代料（不在目录中）
PIC24HJ128GP306T-I/PT
✅ 直接替换✓ 有现货
$6.1 / 个
查看数据手册 →PIC24HJ128GP306AT-E/PT
✅ 直接替换📋 参考替代料（不在目录中）
PIC24HJ128GP306A-E/PT
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$6.1 / 个
查看数据手册 →dsPIC33FJ128GP306A-I/PT
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
PIC24HJ128GP306A-I/MR
✅ 直接替换✓ 有现货
$3.24 / 个
查看数据手册 →PIC24HJ128GP306AT-I/PT 最大额定值与电气特性
| Core Architecture | PIC24H 16-bit modified Harvard |
| Instruction Width | 16-bit (24-bit instruction word) |
| Maximum CPU Speed | 40 MIPS (FOSC up to 80 MHz with PLL) |
| Program Memory (Flash) | 128 KB (43K x 24) |
| Data RAM | 16 KB |
| Operating Voltage (VDD) | 3.0 V to 3.6 V |
| 封装 | 64-pin TQFP (10x10 mm) |
| General-Purpose I/O | 53 |
| UART/USART | 2 channels (IrDA/LIN capable) |
| SPI | 2 channels |
| I2C | 2 channels |
| CAN 2.0b | 2 modules |
| Timers | 4 x 16-bit |
| Parallel Master Port (PMP) | Yes |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
| Lead-Free / Halogen-Free | Yes |
PIC24HJ128GP306AT-I/PT 引脚配置
| 引脚 1 | RP15 — Remappable I/O / digital I/O |
| 引脚 2 | RP14 — Remappable I/O |
| 引脚 3 | RP13 — Remappable I/O |
| 引脚 4 | RP12 — Remappable I/O |
| 引脚 5 | RP11 — Remappable I/O |
| 引脚 6 | RP10 — Remappable I/O |
| 引脚 7 | RP9 — Remappable I/O |
| 引脚 8 | RP8 — Remappable I/O |
| 引脚 9 | RP7 — Remappable I/O |
| 引脚 10 | RP6 — Remappable I/O |
| 引脚 11 | RP5 — Remappable I/O |
| 引脚 12 | RP4 — Remappable I/O |
| 引脚 13 | RP3 — Remappable I/O |
| 引脚 14 | RP2 — Remappable I/O |
| 引脚 15 | RP1 — Remappable I/O |
| 引脚 16 | RP0 — Remappable I/O |
| 引脚 17 | AVSS — Analog ground |
| 引脚 18 | AVDD — Analog supply voltage (3.0V-3.6V) |
| 引脚 19 | AN0 — Analog input / remappable |
| 引脚 20 | AN1 — Analog input / remappable |
| 引脚 21 | AN2 — Analog input / remappable |
| 引脚 22 | AN3 — Analog input / remappable |
| 引脚 23 | AN4 — Analog input / remappable |
| 引脚 24 | AN5 — Analog input / remappable |
| 引脚 25 | VREF+ — ADC positive reference |
| 引脚 26 | VREF- — ADC negative reference |
| 引脚 27 | AVDD — Analog supply |
| 引脚 28 | AVSS — Analog ground |
| 引脚 29 | OSC1 — Crystal/clock input |
| 引脚 30 | OSC2 — Crystal/clock output |
| 引脚 31 | MCLR — Master clear reset (active low) |
| 引脚 32 | SOSCO — Secondary oscillator output |
| 引脚 33 | SOSCI — Secondary oscillator input |
| 引脚 34 | PGEC1 — ICSP clock (debug/programming) |
| 引脚 35 | PGED1 — ICSP data (debug/programming) |
| 引脚 36 | VDD — Digital supply (3.0V-3.6V) |
| 引脚 37 | VSS — Digital ground |
| 引脚 38 | C1IN- — Comparator 1 negative input |
| 引脚 39 | C1IN+ — Comparator 1 positive input |
| 引脚 40 | C2IN- — Comparator 2 negative input |
| 引脚 41 | C2IN+ — Comparator 2 positive input |
| 引脚 42 | PMA0 — Parallel Master Port address 0 |
| 引脚 43 | PMA1 — Parallel Master Port address 1 |
| 引脚 44 | PMA2 — Parallel Master Port address 2 |
| 引脚 45 | PMA3 — Parallel Master Port address 3 |
| 引脚 46 | PMA4 — Parallel Master Port address 4 |
| 引脚 47 | PMA5 — Parallel Master Port address 5 |
| 引脚 48 | PMA6 — Parallel Master Port address 6 |
| 引脚 49 | PMA7 — Parallel Master Port address 7 |
| 引脚 50 | PMD0 — Parallel Master Port data 0 |
| 引脚 51 | PMD1 — Parallel Master Port data 1 |
| 引脚 52 | PMD2 — Parallel Master Port data 2 |
| 引脚 53 | PMD3 — Parallel Master Port data 3 |
| 引脚 54 | PMD4 — Parallel Master Port data 4 |
| 引脚 55 | PMD5 — Parallel Master Port data 5 |
| 引脚 56 | PMD6 — Parallel Master Port data 6 |
| 引脚 57 | PMD7 — Parallel Master Port data 7 |
| 引脚 58 | PMALL — PMP latch low strobe |
| 引脚 59 | PMALH — PMP latch high strobe |
| 引脚 60 | PMRD — PMP read strobe |
| 引脚 61 | PMWR — PMP write strobe |
| 引脚 62 | PMCS1 — PMP chip select 1 |
| 引脚 63 | PMCS2 — PMP chip select 2 |
| 引脚 64 | RB15 — Port B I/O |
典型应用
PIC24HJ128GP306AT-I/PT 适用于 7 应用s: Industrial CAN-bus Node, Automotive LIN Master/Slave Node, TFT-LCD HMI / GUI Controller, Portable Data Acquisition Module, Motor Control (BLDC / PMSM), Building Automation / Sensor Hub, Medical Patient Monitor Peripheral.
Industrial CAN-bus Node
The PIC24HJ128GP306AT-I/PT's two independent CAN 2.0b modules support bit rates up to 1 Mbps, while its 128 KB Flash and 16 KB SRAM allow a full CANopen or J1939 stack to run alongside the application firmware. Compared with 8-bit MCUs, the 16-bit core handles CAN message handling and PID loops deterministically at 40 MIPS, and the 53 GPIO pins free up extras for sensor and actuator interfaces. Drop the part between a 5V CAN transceiver such as the MCP2551 and a sensor cluster, and use the dual UART for RS-485 backup.
推荐
Automotive LIN Master/Slave Node
The PIC24HJ128GP306AT-I/PT integrates LIN-capable UART with hardware break detect and autobaud, making it a strong fit for LIN 2.x body-electronics slaves such as door modules and seat controllers. The industrial -40C to +85C temperature grade covers cabin environments, while the 16-bit DSP-free core keeps deterministic ISR latency for LIN schedule table timing. The 128 KB Flash hosts LIN stack plus diagnostics; the 53 I/O drive H-bridge and switch matrix without external muxes.
推荐
TFT-LCD HMI / GUI Controller
The PIC24HJ128GP306AT-I/PT includes a 16-bit Parallel Master Port (PMP) that connects directly to small TFT-LCD panels and external SRAM/Flash for framebuffers. At 40 MIPS the core drives a 320x240x16-bit LCD refresh alongside keyscan and backlight PWM without DMA, while the dual SPI interfaces handle touch-controller and on-board NOR Flash. Industrial temperature grade and 53 GPIO suit factory-panel HMIs; pair with the internal 4-wire resistive touch controller for a complete BOM.
推荐
Portable Data Acquisition Module
With a 10/12-bit ADC, 16 KB SRAM and low-power Sleep modes, the PIC24HJ128GP306AT-I/PT is well suited to battery-powered multi-channel data loggers. The 40 MIPS core executes FIR averaging in real time on multiple ADC channels, while UART/USART or SPI links push samples to an SD card or BLE companion. The 3.0V-3.6V supply aligns directly with single-cell Li-ion outputs, simplifying power-tree design. Industrial temperature range enables field-deployed instrumentation.
推荐
Motor Control (BLDC / PMSM)
The PIC24HJ128GP306AT-I/PT provides four 16-bit timers with PWM and a 40 MIPS core that handles trapezoidal BLDC commutation and simple scalar control. For space-vector or field-oriented control, migrate to the dsPIC33FJ128GP306A-I/PT drop-in upgrade without PCB rework. Dual analog comparators and the ADC sample current shunts for overcurrent detection, while CAN and LIN enable industrial servo and e-bike integrations.
推荐
Building Automation / Sensor Hub
The PIC24HJ128GP306AT-I/PT integrates two UART, two SPI, and two I2C channels, enabling it to serve as a building-automation hub bridging Modbus, BACnet MS/TP, KNX, and I2C sensor clusters. The 53 GPIO drive relays and digital inputs directly, while 128 KB Flash accommodates the protocol stack plus application logic. Industrial temperature grade allows deployment in plant rooms; pin compatibility with the PIC24HJ256GP506A-I/PT provides headroom for code expansion.
推荐
Medical Patient Monitor Peripheral
The PIC24HJ128GP306AT-I/PT's 53 GPIO and 16-bit timers support multi-channel pulse-oximeter and temperature signal chains, while the 16 KB SRAM is sufficient for moving-window SpO2 algorithms. CAN-bus connectivity lets the module stream data to a central monitor, and the PIC24H core delivers deterministic interrupt handling required by IEC 60601-1-8 alarm timing. Use the UART to drive an isolated RS-485 link for hospital wired networks.
推荐
推荐产品汇总
工程参考数据： PIC24HJ128GP306AT-I/PT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | PIC24HJ128GP306A-I/PT | PIC24HJ128GP306T-I/PT | PIC24HJ128GP306AT-E/PT | dsPIC33FJ128GP306A-I/PT |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 64-TQFP (10x10) | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same |
| Flash | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| RAM | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB |
| CPU Speed | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS | 40 MIPS |
| CAN 2.0b Modules | 2 | 2 | 2 | 2 | 2 |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | -40C to +125C (extended) | -40C to +85C |
| DSP Extensions | No (PIC24H) | No | No | No | Yes (dsPIC33F DSP engine) |
关键差异点
- Dual CAN 2.0b with 8 acceptance filters per module （对比 PIC24FJ128GA006-I/PT)
- Seamless migration to dsPIC33F DSP at same footprint （对比 dsPIC33FJ128GP306A-I/PT)
- PMP parallel master port for direct LCD and external memory （对比 PIC24FJ64GB004-I/PT)
设计说明
The PIC24HJ128GP306AT-I/PT operates from a single 3.0V to 3.6V VDD rail; AVDD must be tied to VDD through a ferrite bead and each AVDD/VDD pin needs its own 0.1 uF ceramic plus a shared 10 uF bulk capacitor. Brown-out reset is programmable via the RCON register to trip between 2.0V and 3.0V; configure it for 3.0V to avoid inrush corruption. Keep the regulator ripple below 30 mV RMS at the MCU pin to maintain ADC accuracy.
Route the 64-TQFP land pattern per JEDEC MO-153 with 0.5 mm pitch; place 0.1 uF decoupling within 3 mm of each VDD pin and a 10 uF bulk on the side closest to the regulator. Keep the ICSP lines (PGEC1/PGED1) as short as possible to enable clean MPLAB ICD 4 or PICkit 4 debug. Keep the ADC analog traces routed parallel over a contiguous ground plane; AVDD ferrite bead should be within 5 mm of the pin. Source: Microchip PIC24HJ128GP306 family PCB design guide.
Do not leave MCLR floating - it must be tied to VDD through a 10 kohm pull-up so spurious resets do not corrupt Flash writes. Avoid configuring PGEC1/PGED1 as GPIO if in-circuit debug is needed. The PMP pins are shared with Port E and F; selecting PMP mode remaps them - verify with the I/O Mapping excel before commit. When migrating from PIC24F, note the PIC24H requires PLL configuration via CLKDIV before the CPU executes at 40 MIPS.
合规信息
RoHS and REACH compliance per Microchip product page; industrial temperature grade is not AEC-Q100 qualified - use AEC-Q100 variants (e.g., PIC24HJ128GP306AT-I/PTC31) when needed.
