PN5321A3HN-C10651 - NFC Controller 13.56MHz, 40-VFQFN | NXP
料号： PN5321A3HN-C10651 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $5.49 | $5.49 |
| 10 | $4.95 | $49.50 |
| 100 | $4.35 | $435.00 |
| 500 | $3.8 | $1,900.00 |
| 1,000 | $3.45 | $3,450.00 |
PN5321A3HN-C10651 概述
NFC controllers, also known as high-frequency RFID reader ICs, form the bridge between a host processor and a contactless smartcard or NFC peer. They modulate the 13.56 MHz carrier, perform anti-collision, and handle the link-layer protocol (ISO 14443-3 for proximity cards, NFCIP-1 for peer-to-peer). Within the broader system hierarchy, the PN532 sits between the application MCU (which runs the user transaction logic) and the antenna matching network, making this IC family a sub-class of RFID transceivers within RF & wireless semiconductors.
Key features include an integrated RF output stage capable of driving a printed or wire loop antenna directly, hardware support for peer-to-peer NFCIP-1 mode, hardware crypto accelerator for MIFARE Classic crypto, and a flexible host interface selector (I2C/SPI/UART). The PN532 implements the full NFC Forum tag reading/writing specification and supports card emulation when paired with an external secure element. Firmware is on-chip (no external MCU code needed for basic read/write).
Architecturally, the PN532 combines a 16 MHz 80C51 core for command processing, dedicated hardware for the 13.56 MHz RF front-end, and SRAM/ROM for the embedded firmware stack. The host MCU communicates through a single wire-selectable interface, while the analog front-end handles load modulation (RX) and 13.56 MHz ASK/OOK modulation (TX) with on-chip output stage rated to drive antennas per ISO/IEC 14443-2.
Typical applications include payment terminals and POS readers, NFC-enabled access control readers, handheld payment terminals, peer-to-peer data exchange devices (Android Beam-style file sharing), and embedded RFID readers for industrial identification. NXP explicitly recommends the PN7120 or PN7150 (full-NCI USB/I2C front-ends) for new designs; PN5321A3HN-C10651 is maintained for legacy designs.
When designing with this device, route the antenna traces as a 50 ohm-controlled differential pair, place the matching network components (typically pi-network of 220 nH/22 pF/220 nH) within 5 mm of the TX1/TX2 pins, and ensure the exposed pad is soldered with at least 8 thermal vias for ground return. Verify host interface voltage compatibility because I2C/SPI/UART signals are not 5V-tolerant on this part.
This page synthesizes distributor pricing, drop-in alternatives (same-brand first, then cross-brand), and practical design notes not found in the manufacturer datasheet. It is intended for engineers maintaining PN532-based products or evaluating long-term availability.
直接替换替代料： PN5321A3HN-C10651 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
PN5321A3HN/C106,55
✅ 直接替换📋 参考替代料（不在目录中）
PN5321A3HN/C106518
✅ 直接替换📋 参考替代料（不在目录中）
PN5321A3HN/C106,55
✅ 直接替换📋 参考替代料（不在目录中）
PN5321A3HN-C10651 规格参数
| RF Type | Read / Write (NFC controller, NFCIP-1 peer-to-peer, card emulation) |
| Operating Frequency | 13.56 MHz |
| Standards Supported | ISO/IEC 14443-A, ISO/IEC 14443-B, ISO/IEC 18092 (NFCIP-1), FeliCa, MIFARE |
| Host Interface | I2C, SPI, UART (selectable via pin) |
| 电源电压 | 2.7 V to 5.5 V |
| 封装 | 40-VFQFN Exposed Pad (HVQFN-40, 6x6 mm) |
| 安装类型 | Surface Mount |
| Processor Core | 80C51 (16 MHz internal) |
| 工作温度 | -30 C to +85 C |
| Storage Temperature | -40 C to +125 C |
| Modulation (TX) | 100% ASK |
| Modulation (RX) | Load modulation, sub-carrier |
| RoHS 状态 | Compliant |
| Lead Free | Yes |
| MSL 等级 | 3 (168 hours) |
PN5321A3HN-C10651 引脚配置
| 引脚 1 | GND — Ground (substrate) |
| 引脚 2 | TX1 — Antenna driver output 1 (differential) |
| 引脚 3 | TX2 — Antenna driver output 2 (differential) |
| 引脚 4 | VMID — Mid-rail reference for RX inputs (decouple to GND) |
| 引脚 5 | RX — Receiver input from antenna matching network |
| 引脚 6 | AVSS — Analog ground |
| 引脚 7 | PVDD — Power for power amplifier / TX drivers |
| 引脚 8 | VBAT — Battery supply input (2.7 V - 5.5 V) |
| 引脚 9 | VDD — Digital supply (decouple 100 nF + 1 uF to GND) |
| 引脚 10 | VCC — Host interface I/O supply |
| 引脚 11 | RSTPD — Reset/Power-down (active high, hold low to enable) |
| 引脚 12 | OSCIN — Crystal oscillator input (27.12 MHz fundamental) |
| 引脚 13 | OSCOUT — Crystal oscillator output |
| 引脚 14 | TEST — Test pin (tie to GND in production) |
| 引脚 15 | SIGOUT — Analog signal output (debug) |
| 引脚 16 | IF0 — Host interface select 0 (I2C/SPI/UART) |
| 引脚 17 | IF1 — Host interface select 1 |
| 引脚 18 | I2C_SDA — I2C data (host interface, I2C mode) |
| 引脚 19 | I2C_SCL — I2C clock (host interface, I2C mode) |
| 引脚 20 | SPI_NSS — SPI chip select (host interface, SPI mode) |
| 引脚 21 | SPI_MOSI — SPI master-out slave-in (host interface) |
| 引脚 22 | SPI_MISO — SPI master-in slave-out (host interface) |
| 引脚 23 | SPI_SCK — SPI clock (host interface) |
| 引脚 24 | UART_TX — UART transmit (host interface, UART mode) |
| 引脚 25 | UART_RX — UART receive (host interface, UART mode) |
| 引脚 26 | IRQ — Host interrupt (active low) |
| 引脚 27 | AUX1 — Auxiliary output 1 (NFCIP-1 peer-mode) |
| 引脚 28 | AUX2 — Auxiliary output 2 (NFCIP-1 peer-mode) |
| 引脚 29 | SDA5V — 5V-tolerant I2C data (external pull-up domain) |
| 引脚 30 | SCL5V — 5V-tolerant I2C clock |
| 引脚 31 | DGND — Digital ground |
| 引脚 32 | DVDD — Digital core supply (1.8 V internal LDO output) |
| 引脚 33 | PWR — Power management control |
| 引脚 34 | AVDD_RF — Analog RF supply (decouple with 100 nF) |
| 引脚 35 | AVDD_ADC — Analog ADC supply |
| 引脚 36 | REF — Internal reference (decouple 10 nF) |
| 引脚 37 | NC — Not connected (per datasheet) |
| 引脚 38 | NC — Not connected (per datasheet) |
| 引脚 39 | NC — Not connected (per datasheet) |
| 引脚 40 | EPAD — Exposed thermal pad (must be soldered to GND) |
典型应用
PN5321A3HN-C10651 适用于 7 应用s: Contactless Payment Terminal (POS), NFC Peer-to-Peer File Exchange, MIFARE Classic Access Control Reader, Industrial RFID Identification Reader, FeliCa Transit Card Reader (Asia-Pacific), NFC-Enabled Accessory / Pairing Device, Public Transit Gate Validator.
Contactless Payment Terminal (POS)
The PN5321A3HN-C10651's integrated MIFARE Crypto1 hardware accelerator and FeliCa support make it a long-validated choice for EMVCo contactless payment terminals. It natively reads ISO 14443-A/B cards at 13.56 MHz and returns demodulated data over I2C/SPI/UART to the payment application MCU. With its 2.7 V to 5.5 V supply range, it drops directly into 3.3 V POS architectures. The 40-VFQFN package keeps the PCB footprint under 36 mm^2, leaving room for the antenna loop and matching network. Compared to NXP's newer PN7150, this part requires no NCI driver port, simplifying legacy terminal firmware maintenance but at the cost of being NRND.
推荐
NFC Peer-to-Peer File Exchange
The PN5321A3HN-C10651 implements the full NFCIP-1 (ISO/IEC 18092) peer-to-peer initiator and target stack on-chip, allowing two NFC devices to exchange small payloads (URLs, business cards, Bluetooth pairing handshakes) without external protocol software. Its 80C51 core handles LLCP/SNEP framing, freeing the host MCU to focus on application data. The exposed-pad QFN package supports the tight PCB layouts required for peer-mode antenna tuning. Read/write distance is typically 5 cm, with peer-mode throughput around 424 kbit/s. Designers should route the TX1/TX2 differential pair with controlled 50 ohm impedance to maintain peer-mode link margin.
推荐
MIFARE Classic Access Control Reader
The PN5321A3HN-C10651 is one of the few ICs with on-chip MIFARE Crypto1 hardware, enabling it to authenticate and read MIFARE Classic sectors at full 106 kbit/s without offloading crypto to the host. This makes it the de-facto reference reader for legacy MIFARE Classic 1K/4K access-control, time-attendance, and transit-card readers. Its 2.7 V to 5.5 V supply directly powers from a single Li-ion cell or 3.3 V regulated rail. The 40-VFQFN footprint is footprint-compatible with NXP's PN512 (no Crypto1) and PN7150 (different pinout), easing reader family design reuse. For new designs, NXP recommends migrating to CLRC663 plus PN7150.
推荐
Industrial RFID Identification Reader
The PN5321A3HN-C10651's -30 C to +85 C industrial operating temperature range and 40-VFQFN rugged package suit factory-floor RFID tag identification readers (parts tracking, WIP management, conveyor sortation). The hardware ISO 14443-A anti-collision stack handles multiple tags simultaneously in the RF zone, and the UART host interface integrates easily with industrial PLCs and HMIs. Its 13.56 MHz carrier propagates well through non-metallic housings. The exposed thermal pad with 8+ thermal vias provides the heat-spreading required for continuous TX operation in unventilated cabinets. Engineers should note the 5V-tolerant I/O restriction when interfacing with 24V PLC systems.
推荐
FeliCa Transit Card Reader (Asia-Pacific)
The PN5321A3HN-C10651's built-in FeliCa (JIS X 6319-4) protocol support at 212 kbit/s and 424 kbit/s makes it the validated reader for Japan and Asia-Pacific transit-card systems (PASMO, Suica, Octopus). Its hardware handles the FeliCa polling and request-response cycle, returning decoded block data to the host. The 40-VFQFN exposed-pad package and 2.7 V to 5.5 V supply suit the compact, battery-powered handheld transit validators used by ticket inspectors. Designers should pair the PN532 with a wide-bandwidth 13.56 MHz antenna tuned for FeliCa's 10 cm read range to maximize passenger throughput at gates.
推荐
NFC-Enabled Accessory / Pairing Device
The PN5321A3HN-C10651 is widely used in Bluetooth pairing accessories - a tap against the NFC reader instantly exchanges the BT MAC address and pairing token, eliminating the manual PIN dance. The PN532 handles the NFC Forum NDEF formatting on-chip, so the host MCU just receives a parsed BT pairing payload over UART. Its small 6x6 mm package fits inside enclosures as small as key fobs. Power consumption during continuous polling is low enough for coin-cell designs with duty-cycled reads. For new designs, the PN7150 + Linux/Android NCI stack delivers the same UX with a modern driver model.
推荐
Public Transit Gate Validator
The PN5321A3HN-C10651's hardware ISO 14443 and FeliCa support, combined with its anti-collision stack, allow turnstile and gate validators to read multiple card types (MIFARE, FeliCa, Calypso) at 13.56 MHz with sub-second transaction times. The 40-VFQFN exposed-pad package provides the thermal headroom for continuous-reader operation in outdoor, unventilated gate housings. The host interface (I2C/SPI/UART) connects to gate controllers that aggregate multiple PN532 readers per gate. Engineers should use shielded coax for the antenna feed to maintain read-range margin across the gate width, and ground the exposed pad with at least 8 thermal vias to a solid ground pour.
推荐
推荐产品汇总
工程参考数据： PN5321A3HN-C10651 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | PN5321A3HN/C106,55 | PN5321A3HN/C106518 |
|---|---|---|---|
| Package | 40-VFQFN Exposed Pad (HVQFN-40, 6x6 mm) | 40-VFQFN Exposed Pad (HVQFN-40, 6x6 mm) - same | 40-VFQFN Exposed Pad (HVQFN-40, 6x6 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors (via Rochester Electronics) |
| Operating Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Host Interface | I2C / SPI / UART | I2C / SPI / UART | I2C / SPI / UART |
| Supply Voltage | 2.7 V to 5.5 V | 2.7 V to 5.5 V | 2.7 V to 5.5 V |
| Standards Supported | ISO 14443-A/B, ISO 18092 (NFCIP-1), FeliCa, MIFARE | ISO 14443-A/B, ISO 18092, FeliCa, MIFARE | ISO 14443-A/B, ISO 18092, FeliCa, MIFARE |
| MIFARE Crypto1 Hardware | Yes | Yes | Yes |
| Lifecycle Status | NRND | NRND | NRND (trace stock) |
| 1k-Unit Price (USD) | $3.45 | $3.45 (Mouser) | $4.20 (Rochester, trace stock) |
关键差异点
- On-chip MIFARE Crypto1 hardware （对比 PN5120A0HN/C106 (pin-compatible but no MIFARE crypto))
- Embedded 80C51 firmware - no host NFC stack needed （对比 PN7150A0HN/C11002 (NCI-compliant, requires host driver))
- Three host interfaces in one IC （对比 Single-interface HF readers (e.g., MFRC52202HN1: SPI only))
设计说明
Route the antenna traces (TX1/TX2) as a 50-ohm controlled-impedance differential pair on the top layer, and place the matching network (typically 220 nH - 22 pF - 220 nH pi-network) within 5 mm of the TX1/TX2 pins. The exposed thermal pad must be soldered to a continuous ground pour with at least 8 thermal vias to provide the RF ground return; failing to do this degrades read range by up to 30%. Keep digital signal traces at least 2 mm away from the antenna loop to avoid coupling noise into the receiver.
Decouple VDD with a 100 nF ceramic capacitor within 5 mm of the pin, plus a 1 uF bulk capacitor. PVDD (power amplifier supply) requires its own 100 nF + 10 uF decoupling network to prevent TX current spikes from disturbing digital supply. The PN5321A3HN-C10651 is NOT 5V-tolerant on host interface pins when VCC is at 3.3 V - add a level shifter (e.g., TXB0104) for mixed-voltage hosts. Hold RSTPD low during power-up until all rails are valid for at least 10 ms.
Do not assume the PN5321A3HN-C10651 is firmware-compatible with NXP's NCI-compliant PN7150/PN7120 - the host command set differs significantly and a port effort is required. Always select the host interface (I2C/SPI/UART) by pin-strapping IF0/IF1 at power-up; these pins are sampled only on reset. Avoid driving the IRQ pin from external sources; it is an open-drain output. When migrating from prototype to production, re-tune the antenna matching because PCB laminate, copper weight, and enclosure materials all shift the resonant frequency.
合规信息
RoHS and lead-free per NXP product page. AEC-Q100 not applicable - PN532 is consumer/industrial grade, not AEC-Q100 qualified. Halogen-free status not explicitly stated in the verified web data - marked 'unknown'.
