PS8936 - 32Gbps PCIe Gen5 x16 Retimer | Parade Technologies
料号： PS8936 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
PS8936 概述
What is a retimer? A retimer is a mixed-signal device placed in series on a high-speed serial link that reconditions a degraded signal using a Clock and Data Recovery (CDR) circuit and re-transmits a clean, retimed waveform to the next segment. Retimers sit between simple redrivers (which are analog equalizers without CDR) and protocol-aware re-drivers; they add link-training transparency and a small, deterministic latency while fully recovering the eye diagram across long PCB traces, backplanes, or cables. PS8936 belongs to the signal-conditioning IC family within the broader high-speed serial interface IC category used in PCIe, CXL, USB, SATA, and Ethernet platforms.
Key features include 16 bidirectional lanes (32 channels total), PCIe 5.0 compliance at 32 GT/s, CXL 1.1/2.0 support, backward compatibility with PCIe 1.0/2.0/3.0/4.0 data rates, a low-latency forwarding path demonstrated as best-in-class in 2023, and integrated link training. The device is offered as PS8936BGA354GTR-A1 in tape-and-reel packaging and is supported by a PS8936-EVB evaluation board and a PS8936-DEBUG BOARD reference design. It is qualified on the PCI-SIG integrator list as a PCIe Gen5 x16 32 Gbps retimer, simplifying compliance validation for OEMs.
Typical applications include AI accelerator and GPU server backplanes, NVMe Gen5 storage controllers, CXL type-3 memory pooling switches, hyperscale rack-scale fabrics, workstation motherboards with multi-slot PCIe Gen5 topologies, and accelerator card risers that need long reach over the top of the board. Its low-latency behavior matters for coherent memory and accelerator fabrics where every nanosecond added by conditioning reduces effective bandwidth.
When designing with PS8936, pay close attention to PCB stack-up, reference-clock routing, and decoupling; the 354-ball BGA package demands a symmetrical escape pattern and a contiguous ground reference. Pair it with a low-jitter 100 MHz reference clock and follow the reference schematic in the PS8936-EVB evaluation kit to ensure first-pass compliance.
This page synthesizes distributor availability, parametric alternatives, paired with practical PCB and thermal design notes that go beyond the manufacturer datasheet, helping engineers evaluate the PS8936 for next-generation Gen5 platforms.
直接替换替代料： PS8936 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： PS8936 （相同外形与封装尺寸） ——差异在于 Function, Maximum Data Rate, Package.
快速对比工具——选择替代料号进行并排对比：
PS8936BGA354GTR-A1
✅ 直接替换📋 参考替代料（不在目录中）
PS8926
✅ 直接替换✓ 有现货
$55.8 / 个
查看数据手册 →PS8926A
✅ 直接替换📋 参考替代料（不在目录中）
PS8936-DBG
✅ 直接替换📋 参考替代料（不在目录中）
PS8936-EVB
✅ 直接替换📋 参考替代料（不在目录中）
PS8936 规格参数
| 功能 | PCI Express Gen 5 / CXL 16-lane retimer |
| Number of Lanes | 16 bidirectional (32 data channels) |
| Maximum Data Rate | 32 Gbps (PCIe Gen 5) |
| Backward-Compatible Data Rates | 2.5 / 5 / 8 / 16 Gbps |
| Supported Protocols | PCIe 5.0, CXL 1.1, CXL 2.0 |
| Direction | Bidirectional |
| 封装 | 354-ball BGA |
| Orderable Part Number | PS8936BGA354GTR-A1 |
| Packaging | Tape and Reel |
| PCI-SIG Compliance | Listed as PCIe5 x16 32 Gbps retimer |
| Evaluation Board | PS8936-EVB |
| Debug Board | PS8936-DEBUG BOARD |
PS8936 354-ball bga 引脚配置指南
PS8936（354-ball bga 封装）的引脚配置。 引脚编号、功能和连接图在制造商数据手册中定义。请参阅该手册以了解确切的封装尺寸和焊接指南。
暂无详细引脚数据： PS8936.
请参阅 数据手册 以查看完整引脚配置。
典型应用
PS8936 适用于 6 应用s: AI Accelerator Server Backplanes, Enterprise NVMe Gen5 Storage Controllers, CXL Type-3 Memory Pooling Switches, Hyperscale Rack-Scale Fabric Interconnects, Workstation Motherboards with Multi-Slot Gen5 Topology, Accelerator Card Risers and Add-In Cards.
AI Accelerator Server Backplanes
The PS8936's 16 bidirectional lanes at 32 Gbps with low-latency forwarding make it ideal for AI training systems that need x16 PCIe Gen5 connectivity between GPUs, NVMe Gen5 storage, and CXL memory pools. Per StorageNewsletter 2023-08-04, PS8936 demonstrated the lowest latencies in the industry for a Gen5 retimer, a critical factor in coherent accelerator fabrics where every nanosecond of added conditioning reduces effective bandwidth. Reference design: PS8936-EVB.
推荐
Enterprise NVMe Gen5 Storage Controllers
The PS8936 supports PCIe 5.0 at 32 GT/s with backward compatibility to PCIe 1.0/2.0/3.0/4.0 data rates, making it ideal for enterprise NVMe Gen5 storage controllers that must interface with both new host CPUs and legacy backplanes. Its 32 data channels enable full x16 host-facing links while maintaining signal-integrity margins over long M.2-to-PCIe adapter traces common in dense storage enclosures.
推荐
CXL Type-3 Memory Pooling Switches
The PS8936 supports Compute Express Link (CXL) 1.1 and 2.0 alongside PCIe 5.0, enabling CXL type-3 memory pooling switches that aggregate DRAM and persistent memory across a rack. Per the StorageNewsletter 2023-01-26 announcement, the PS8936 retimer was specifically developed for PCIe 5.0 and CXL, giving system designers a single retimer that covers both protocols without separate silicon.
推荐
Hyperscale Rack-Scale Fabric Interconnects
The PS8936's 32 Gbps per lane and low-latency forwarding path suit hyperscale rack-scale fabrics that disaggregate compute, memory, and storage. Each retimer instance recovers a clean eye diagram across backplane connectors and long traces, allowing Gen5 signaling to traverse distances that would otherwise force a downgrade to Gen4 - directly preserving rack-level bandwidth density for cloud providers.
推荐
Workstation Motherboards with Multi-Slot Gen5 Topology
The PS8936's 16-lane configuration is ideal for workstation motherboards that need multiple Gen5 x16 slots for GPUs and accelerators. Per the Parade product brief, it is targeted at applications incorporating high lane count PCIe bus widths such as workstations. The BGA-354 package supports dense PCB escape patterns needed for multi-slot topologies.
推荐
Accelerator Card Risers and Add-In Cards
The PS8936 enables long-reach PCIe Gen5 signaling on accelerator card risers and add-in cards where the host slot sits far from the local silicon. CDR-based signal recovery restores the eye diagram across PCB bends and connector crossings that would otherwise exceed Gen5 loss budgets. Reference design PS8936-EVB demonstrates a typical riser implementation with the 354-ball BGA.
推荐
推荐产品汇总
工程参考数据： PS8936 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | PS8936BGA354GTR-A1 | PS8926 | PS8926A | PS8936-DBG | PS8936-EVB |
|---|---|---|---|---|---|---|
| Package | BGA-354 | BGA-354 - same | BGA-354 - same | BGA-354 - same | BGA-354 - same | BGA-354 - same |
| Brand | Parade Technologies | Parade Technologies | Parade Technologies | Parade Technologies | Parade Technologies | Parade Technologies |
| PCIe Generation | Gen 5 | Gen 5 | Gen 4 | Gen 4 | Gen 5 | Gen 5 |
| Maximum Data Rate | 32 Gbps | 32 Gbps | 16 Gbps | 16 Gbps | 32 Gbps | 32 Gbps |
| Number of Lanes | 16 bidirectional | 16 bidirectional | 16 bidirectional | 16 bidirectional | 16 bidirectional | 16 bidirectional |
| CXL Support | Yes (CXL 1.1/2.0) | Yes | No (PCIe only) | No (PCIe only) | Yes | Yes |
| Function Type | Retimer | Retimer | Retimer | Retimer | Retimer (debug) | Evaluation board |
| PCI-SIG Listed | Yes | Yes | Yes (Gen4) | Yes (Gen4) | Yes | Yes |
关键差异点
- PCIe Gen 5 and CXL 1.1/2.0 dual-protocol support （对比 PS8926)
- 16 bidirectional lanes (32 data channels) （对比 PS8580)
- Best-in-class low-latency forwarding （对比 PS8926A)
- Production-grade tape-and-reel variant available （对比 PS8936-DBG)
设计说明
The PS8936 ships in a 354-ball BGA package requiring a symmetrical escape pattern and a contiguous ground reference. Route all 32 high-speed differential pairs with matched lengths within the budget specified in the PS8936-EVB reference design. Use a 4-6 layer stack-up with low-loss dielectric (Df < 0.005 at 8 GHz) to preserve Gen5 eye margins.
Provide a low-jitter 100 MHz reference clock with phase noise below -120 dBc/Hz at 10 kHz offset. Place the reference clock generator within 25 mm of the PS8936 clock input pins and maintain 50 ohm single-ended impedance. Reference-clock jitter directly multiplies into retimer output jitter and will close the Gen5 link-training eye.
Estimated: at 32 Gbps across 32 active channels with typical 8 pJ/bit power, the PS8936 dissipates approximately 8 W under full bidirectional load. Provide a thermal pad array beneath the BGA connected to an inner ground plane, and ensure 200 LFM of airflow or attach a small heatsink to keep junction temperature below 105 C.
Decouple each power rail with 0.1 uF X7R ceramic capacitors placed within 2 mm of the BGA balls, plus bulk 10 uF and 22 uF capacitors per rail. Separate analog and digital ground returns to a single star point beneath the IC. Avoid routing any high-speed lanes across plane splits, which would severely degrade Gen5 return loss.
Do not substitute a redriver for the PS8936 on long PCIe Gen5 traces - redrivers lack CDR and will fail compliance on lossy channels. Always validate the design with the PS8936-EVB schematic and PCB layout before tape-out, and verify with a PCIe Gen5 compliance test load at your test house.
合规信息
RoHS, REACH, lead-free, halogen-free and AEC-Q100 status not disclosed in the public Parade product page or PCI-SIG listing as of 2026-10-15. Contact Parade Technologies directly for full material-declaration documents. AEC-Q100 not applicable - this is a high-speed server/storage interface IC, not an automotive-grade part.
