ADC/DAC
المنتجات (3,100+)
LTC1605CN#PBF - 16-Bit 100ksps SAR ADC, ±10V Bipolar | ADI
The Analog Devices (formerly Linear Technology) LTC1605CN#PBF is a 100 ksps, 16-bit sampling analog-to-digital converter (ADC) that draws only 55 mW (typical) from a single 5 V supply, housed in a 28-pin PDIP (through-hole) package. The device integrates a sample-and-hold front end, a precision buried-zener reference, a switched-capacitor successive-approximation ADC core, and a trimmed internal clock, providing a complete data-acquisition front end in one IC. A successive-approximation register (SAR) ADC is a precision converter architecture that performs a binary search across an internal DAC for each conversion, achieving deterministic low-latency (one conversion cycle) results with no pipeline delay. SAR ADCs are widely used in industrial, instrumentation, and process-control applications where DC accuracy, high linearity, and excellent AC performance at moderate sampling rates are required. The LTC1605 sits in the precision SAR family alongside the 14-bit LTC1410 and 12-bit LTC1290, sharing a common analog front-end philosophy and pinout philosophy. Key specifications include 16-bit resolution with no missing codes, ±2.0 LSB maximum integral nonlinearity (INL), ±10 V true-bipolar input range from a single 5 V supply, 100 ksps sampling rate, and 55 mW typical power dissipation. The integrated reference eliminates external reference components, simplifying the bill of materials. The parallel data interface allows direct connection to microprocessors, FPGAs, or DSPs without serial-deserialization glue logic. Typical applications include industrial process control, multiplexed data-acquisition systems, precision instrumentation, seismic and weigh-scale digitizers, spectrum and vibration analysis front ends, and bench-top DMM front ends. The ±10 V true-bipolar input is a key differentiator, allowing direct digitization of industrial sensor outputs (4-20 mA loops scaled to voltage, strain-gauge bridges, thermocouple amplifiers) without external signal conditioning. When designing with the LTC1605, allocate at least 8 analog input pins plus dedicated AGND and DGND pins, and follow ADI's recommended four-layer board with separate analog and digital ground planes joined at a single point near the IC. The internal reference requires a 10 µF bypass capacitor on the REFCOMP pin for optimal linearity. This page synthesizes distributor pricing, drop-in 28-PDIP alternatives (LTC1605IN, LTC1605-1CN, LTC1605-2CN), and practical design notes not aggregated on any single manufacturer or distributor page.
LTC1650AIN#PBF - 16-Bit Low-Glitch Voltage Output DAC | ADI
The Analog Devices LTC1650AIN#PBF is a 16-bit, low-glitch, rail-to-rail voltage-output digital-to-analog converter (DAC) housed in a 16-pin PDIP through-hole package, qualified to the industrial -40C to +85C temperature range. It integrates a precision R-2R ladder, an output buffer amplifier, and a three-wire cascadable serial (SPI/MICROWIRE-compatible) interface, delivering 16-bit monotonic performance over temperature with a glitch impulse of just 2 nV-s. The DAC operates from dual plus/minus 5 V supplies and dissipates approximately 50 mW, with the output swing defined by REFLO and REFHI reference inputs that can be tied for unipolar or bipolar modes. A digital-to-analog converter (DAC) is a data-conversion integrated circuit that translates a digital code word into a precisely scaled analog voltage or current. Within the broader data-converter family (ADC and DAC), this part belongs to the precision narrow-DC voltage-output DAC category, sitting under the hierarchy: DAC -> data converter -> mixed-signal IC -> semiconductor. The LTC1650AIN#PBF specifically targets low-glitch, low-noise, buffered voltage-output applications where a clean step transition and rail-to-rail swing are critical. Key differentiating specifications include 2 nV-s glitch impulse, 30 nV/sqrt(Hz) noise spectral density, 16-bit guaranteed monotonicity, and a true rail-to-rail output buffer that swings to within millivolts of either supply rail. The cascadable three-wire serial interface allows multiple LTC1650 devices to share a single SPI bus by daisy-chaining the DOUT pin into the next device's DIN pin, simplifying multi-axis or multi-channel designs. Architecturally, the device combines a thin-film R-2R ladder network for INL/DNL linearity with an on-chip output op-amp capable of driving 2 kohm/100 pF loads. The internal reference inputs (REFHI/REFLO) decouple the output range from the supply rails, enabling asymmetric spans such as 0 to 4.096 V for unipolar or plus/minus 4.096 V for bipolar operation. Typical applications include industrial process control calibration, automated test equipment (ATE) waveform generation, digitally controlled offset and gain trimming, programmable voltage references, and motor-control setpoint generation. The wide output swing and low glitch make the LTC1650AIN#PBF a strong fit where each code transition must not couple into downstream signal-chain stages. When designing with this part, place 0.1 uF decoupling capacitors close to AVDD, DVDD, and AVSS pins and route REFHI/REFLO traces as a differential pair. Keep the analog ground (AGND) and digital ground (DGND) joined at a single star point beneath the IC to preserve the 16-bit linearity. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical PCB-level design guidance not found in the manufacturer datasheet alone, giving engineers a single reference for evaluation and sourcing.
LTC1657LIGN - 16-Bit Rail-to-Rail DAC, 28-SSOP | Analog Devices
The Analog Devices LTC1657LIGN is a 16-bit rail-to-rail micropower parallel digital-to-analog converter (DAC) housed in a 28-lead SSOP (GN) package. It operates from a single 2.7 V to 5.5 V supply, delivers monotonic 16-bit performance over the industrial temperature range, and provides a deglitched rail-to-rail voltage output stage that swings within 8 mV of either rail. Typical supply current is 650 uA, making it one of the lowest-power 16-bit parallel DACs in its class. A digital-to-analog converter (DAC) is an integrated circuit that converts a digital code word into a precisely defined analog voltage or current. Within the broader signal-chain taxonomy, the LTC1657 belongs to the precision converter family -> data converter -> mixed-signal IC -> semiconductor. The LTC1657 specifically targets low-power, high-resolution applications where a parallel microprocessor-style interface is preferred for fast code updates without serial-clock overhead. Key features include guaranteed 16-bit monotonicity over temperature, maximum DNL of ±1 LSB, internal power-on reset to zero scale, an asynchronous CLR pin for output forcing, and a built-in 1.25 V reference accessible at the REFOUT pin (LTC1657L variant). The device accepts a parallel 16-bit word and updates the output on the rising edge of CS/WR. Settling time to ±1 LSB is specified at 20 us for a full-scale step. The SSOP-28 footprint is industry-standard and compatible with the LTC1450 12-bit family, providing an upgrade path for existing designs. Architecturally, the LTC1657LIGN uses a resistor-string (R-2R ladder) topology with an output buffer amplifier, ensuring inherently monotonic operation and low glitch impulse. The reference input can be driven externally or tied to the internal 1.25 V bandgap via REFOUT, providing design flexibility for both ratiometric and absolute-output applications. Typical applications include industrial process control, digital offset and gain adjustment, automatic test equipment (ATE) programmable stimulus, audio attenuators with parallel volume control, and portable battery-powered instrumentation where the 650 uA quiescent current extends operating life. The wide supply range and rail-to-rail output maximize signal swing on low-voltage rails. When designing with this device, ensure the REFLO pin is tied to GND and that bypass capacitors of 0.1 uF and 10 uF are placed close to VCC. The asynchronous CLR pin must be held high during normal operation to avoid unintended reset events. Designers migrating from the LTC1450 12-bit family benefit from pin-compatibility and only need to extend the data bus from 12 to 16 bits. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single source for evaluation, sourcing, and PCB layout reuse.
LTC1740CG - 14-Bit 6Msps Sampling ADC | Analog Devices
The Analog Devices LTC1740CG is a 14-bit, 6Msps sampling analog-to-digital converter with one pipelined input, a parallel interface, and a 36-SSOP package. It operates from a single 5V supply or dual ±5V supplies and consumes 245mW, making it suitable for compact data-acquisition and signal-processing systems. The converter supports differential full-scale input ranges of ±2.5V and ±1.25V with its internal precision reference. A sampling ADC is a mixed-signal integrated circuit that samples an analog voltage and converts it into a digital code. The LTC1740CG belongs to the ADC and DAC hierarchy, combining an input sample-and-hold circuit, a 14-bit conversion stage, a programmable reference, and a parallel digital interface in one device. This integration reduces external component count and simplifies the connection between analog inputs and digital processors or programmable logic. The device converts at 6Msps while providing 79dB signal-to-noise plus distortion ratio and 91dB spurious-free dynamic range at a 2.5MHz input frequency. Its differential nonlinearity is 0.5LSB, and its integral nonlinearity is less than 1LSB. The sampling system has an 80MHz full-power bandwidth, allowing designers to evaluate dynamic performance and antialiasing requirements across a broad input-frequency range. Power architecture is another important feature. A single 5V rail simplifies conventional positive-supply designs, while dual ±5V operation supports bipolar analog signal chains. The 245mW power consumption is suitable for portable and embedded instrumentation when paired with careful thermal and layout design. The flexible input circuit can also accept other full-scale ranges when an external reference is used. Typical applications include industrial process monitoring, medical instrumentation, communications receivers, automated test equipment, and digital oscilloscope or waveform-capture front ends. The parallel output allows direct connection to an FPGA, CPLD, DSP, or other high-speed digital acquisition logic. When laying out the circuit, place the input, reference, and decoupling connections close to the device and maintain a controlled return path for the analog input. Check the converter’s supply sequencing, output coding, clocking, and acquisition timing requirements in the manufacturer datasheet before connecting it to a capture system. This page combines the manufacturer specifications with practical application guidance for engineers evaluating the LTC1740CG.
LTC1855IG - 14-Bit 8-Channel 100ksps ADC | Analog Devices
Analog Devices LTC1855IG is an 8-channel, 14-bit, 100ksps successive-approximation analog-to-digital converter with shutdown support, operated from a single 5V supply and packaged in a 28-pin SSOP. The device accepts input signals within the ±10V family range and provides a programmable multiplexer for single-ended inputs and differential pairs. An ADC is an interface IC that converts continuous analog voltage into a numeric representation for measurement, control, monitoring, or recording systems. The ADC belongs to the data-converter hierarchy, where it sits between sensors or signal-conditioning circuits and a microcontroller, DSP, FPGA, or industrial controller. Its purpose is to provide repeatable digital measurements while preserving the voltage relationships present at its analog inputs. The LTC1855 family combines 12-bit, 14-bit, and 16-bit resolution options with a common eight-channel multiplexing architecture. The LTC1855 specifically provides ±1.5LSB integral nonlinearity, a trimmed internal clock, a maximum conversion time of 5µs, and a guaranteed sampling rate of 100ksps. Shutdown capability allows the converter to reduce power use when continuous acquisition is unnecessary. Internally, the converter uses a successive-approximation conversion technique and a serial output architecture. Its eight-input multiplexer reduces the need for separate converter channels when several analog signals must be measured sequentially. The internal clock is trimmed to maintain consistent conversion timing, while the single 5V supply simplifies system power architecture compared with converters requiring separate analog and digital rails. Typical applications include industrial process monitoring, multichannel sensor acquisition, data logging, laboratory instrumentation, factory automation, and embedded measurement systems. The 28-pin SSOP package can support compact controller boards, although analog routing, reference grounding, input conditioning, and digital interface timing require careful PCB layout. Designers should verify the complete pin description and electrical limits in the manufacturer datasheet before assigning connector or signal-ground pins. Input protection, source impedance, acquisition time, reference quality, and digital clock timing can materially affect code accuracy even when the converter's nominal resolution and conversion rate meet the application requirement. This product page combines the confirmed 14-bit resolution, eight-channel multiplexing, 100ksps throughput, ±10V input classification, single 5V operation, shutdown function, and SSOP packaging with practical guidance for selecting a compatible replacement and integrating the converter into a multichannel analog measurement system.
LTC1856IG - 16-Bit, 100ksps, 8-Ch ±10V ADC | Analog Devices
The Linear Technology/Analog Devices LTC1856IG is a 16-bit, 100 ksps, 8-channel successive-approximation analog-to-digital converter (SAR ADC) housed in a 28-pin SSOP (G) package. According to the Analog Devices LTC1854/LTC1855/LTC1856 datasheet, the device operates from a single 5 V supply, integrates an 8-channel analog input multiplexer programmable for single-ended inputs, differential pairs, or a combination of both, and provides ±30 V fault protection on every channel so that a transient on one channel does not disturb conversions on the remaining channels. A successive-approximation register (SAR) ADC is a type of data converter that performs a binary search through an internal capacitive DAC to resolve an analog input in N clock cycles, where N is the resolution in bits. SAR ADCs offer deterministic latency, no pipeline delay, and excellent DC accuracy, which makes them well suited for multiplexed data-acquisition systems, industrial process control loops, and instrumentation that scans many channels at modest rates. The LTC1856 sits inside this hierarchy as a low-power, multi-channel, 16-bit precision SAR converter with integrated input protection. Key specifications include 16-bit resolution (LTC1856) within the LTC1854/55/56 family, ±3 LSB maximum INL for the LTC1856, a 5 µs maximum conversion time, a 100 ksps guaranteed sampling rate, single 5 V supply operation, and an integrated shutdown mode for power-sensitive multiplexed applications. The internal oscillator is trimmed for low aperture uncertainty and consistent conversion timing across the operating range. The 8-channel multiplexer is software-configurable for 8 single-ended inputs, 4 differential pairs, or any mixed combination; a fault on any one input channel does not corrupt conversions on the others because each input is independently over-voltage protected to ±30 V. A hardware shutdown pin reduces supply current between conversions for battery-powered or thermocouple-scanning systems. Typical applications include industrial process control and SCADA data acquisition modules, multi-channel thermocouple and RTD temperature monitoring with cold-junction compensation, portable and bench-top multi-meter instruments, multichannel analog front-ends for PLCs, and automated test equipment requiring 16-bit DC accuracy across many input ranges. The ±10 V true-bipolar input range (with 5 V supply) makes the LTC1856IG drop-in compatible with the output swing of legacy ±10 V instrumentation and industrial sensors. When designing with this ADC, add a 10 µF/0.1 µF bypass pair on the 5 V pin and place the part close to the analog input protection network. Use a low-impedance input buffer for high source-impedance sensors to preserve 16-bit accuracy. The internal reference must be decoupled per the datasheet to avoid gain error; an external reference can be driven if higher accuracy or a lower temperature coefficient is required. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer's datasheet, including verified 28-SSOP footprint cross-references and a side-by-side specification comparison.
LTC1857IG - 8-Channel 12-Bit 100ksps ADC | Analog Devices
The Analog Devices LTC1857IG is an 8-channel, 12-bit, 100ksps successive-approximation analog-to-digital converter with programmable input ranges of 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V. The industrial-temperature device operates from a single 5 V supply and is packaged in a 28-lead SSOP. An analog-to-digital converter is an interface IC that converts continuous analog voltages into numerical values for processing by a microcontroller, DSP, or other digital control system. The LTC1857 belongs to the ADC hierarchy, where resolution, conversion rate, input bandwidth, channel count, and interface characteristics determine the measurement precision and throughput available to the end system. The LTC1857 combines an eight-channel multiplexer, 12-bit conversion resolution, and a sampling rate of 100ksps. Its input multiplexer can be configured for single-ended signals or differential input pairs. Programmable unipolar and bipolar ranges support industrial sensor acquisition, process-control signals, and bipolar measurement systems without requiring a separate external range-selection circuit. The converter includes an onboard high-performance sample-and-hold circuit and precision reference, which minimize external component requirements. Its stated power dissipation is 40 mW, and two user-selectable shutdown modes help reduce consumption when the acquisition system does not require continuous conversion. The LTC1857 is specified at ±1 LSB integral nonlinearity. Typical applications include eight-channel industrial data acquisition, thermocouple and transducer interfaces, factory monitoring, process-control equipment, and embedded measurement systems. Its software-programmable input ranges are particularly useful when one ADC must support several sensors operating across different voltage scales. Design the input network to preserve the selected range and provide suitable settling between multiplexer transitions. Maintain adequate bypass capacitance at the 5 V supply and use the manufacturer pin-description table when assigning analog, digital, reference, and shutdown connections. Verify timing, acquisition sequencing, and overvoltage conditions in the final system. This page organizes the LTC1857IG specifications, verified drop-in alternatives, input-range guidance, and practical design considerations into a compact engineering reference for selecting, purchasing, and implementing the converter.
LTC2107IUK - 16-Bit 210Msps High-Performance ADC | Analog Devices
The Analog Devices LTC2107IUK is a 16-bit, 210 Msps high-performance pipelined analog-to-digital converter (ADC) housed in a 48-pin QFN (7x7 mm, exposed pad) package, designed specifically for the most demanding receiver applications such as software-defined radio (SDR) and multi-channel GSM base stations. Combining high sample rate, low noise and high linearity, the part delivers SNR = 80 dBFS and an industry-leading SFDR performance that enables a new generation of direct-sampling digital radio designs. What is a high-speed pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture that converts an analog input by passing the signal through a cascade of low-resolution flash sub-converter stages, each resolving a few bits and feeding the residue to the next stage. Pipelined ADCs sit within the broader hierarchy of Nyquist-rate data converters (successive-approximation, flash, pipelined) and serve as the workhorse for widebandwidth communications, instrumentation and radar signal chains that demand both high sampling rate and 12-16 bit resolution. Key features of the LTC2107IUK include differential input architecture optimized for IF sampling, 210 Msps conversion rate, on-chip buffer and programmable digital gain, low-jitter clock interface accepting CMOS/LVDS/ PECL inputs, and LVDS/SPI-configurable output modes for flexible data capture. The 80 dBFS SNR and high spurious-free dynamic range ensure clean digitization of multi-carrier waveforms without raising the receiver noise floor. Architecturally, the LTC2107IUK integrates a precision front-end sample-and-hold, multi-bit pipelined core, on-chip voltage reference, and output error correction. The exposed-pad QFN-48 package provides a low thermal resistance path (~30 C/W θJA on a 4-layer JEDEC PCB) so the part can sustain full-speed operation in dense radio boards without external heatsinking. Typical applications include software-defined radio receivers, multi-carrier GSM/EDGE and LTE base-station receivers, broadband instrumentation, radar/EW intermediate-frequency digitization, and high-speed medical imaging front-ends. The wide input bandwidth and direct IF sampling capability let designers replace traditional analog mixer/IF-filter chains with a single ADC at lower BOM cost. When designing with the LTC2107IUK, pay attention to input common-mode voltage, transformer coupling, and clock jitter. An aperture jitter of 200 fs RMS guarantees SNR at full-rate input frequencies; designers must keep total system clock jitter below ~500 fs RMS to preserve dynamic range. A 4-layer PCB with continuous ground plane and proper LVDS output routing is essential for EMI compliance.
LTC2122CUK - Dual 14-bit 170Msps ADC with JESD204B | ADI
The Analog Devices LTC2122CUK is a dual 14-bit 170Msps analog-to-digital converter with JESD204B serial outputs, housed in a 48-pin QFN (7x7 mm) package. It supports 2-channel simultaneous sampling at up to 170Msps per channel, with 70dBFS SNR and 90dBFS spurious-free dynamic range (SFDR) for high-frequency, wide dynamic range signal acquisition. What is a JESD204B ADC? JESD204B is a high-speed serial interface standard (JEDEC JESD204B, revision 2011) that converts parallel ADC data into serialized lanes running at multi-gigabit rates. It reduces PCB routing congestion by replacing wide parallel LVDS buses with 1-8 differential lanes, simplifying layout for multi-Gsps converters used in communications, radar, and test instrumentation. As a pipelined dual-channel converter with serial outputs, the LTC2122CUK sits in the hierarchy: ADC -> data converter -> signal chain IC -> semiconductor. Key features include a 1.25GHz analog input bandwidth that enables reliable IF under-sampling, integrated input buffers to ease front-end matching, and sub-clock jitter performance optimized for communications transceivers. The pipelined architecture delivers low latency and deterministic sample timing across both channels, simplifying multi-channel synchronization in MIMO and phased-array systems. Technical depth: the LTC2122CUK uses a calibrated pipelined core per channel with on-chip dither, achieving 70dBFS SNR and 90dBFS SFDR with input tones in the Nyquist zone. The JESD204B subclass 1 interface supports deterministic latency and supports 1 to 4 lanes per ADC, with link speeds up to 4.5Gbps per lane depending on configuration. The 7x7 mm QFN-48 package exposes a thermal pad for low-junction-rise operation. Typical applications include multi-channel wireless communications receivers, multiband radar and phased-array digitizers, broadband data acquisition systems, and high-end test and measurement instrumentation. The dual-channel simultaneous-sampling capability is particularly valuable in diversity receivers and I/Q signal paths. When designing with this part, ensure the JESD204B link parameters (L, M, F, K) match the receiving FPGA or ASIC SerDes, and provide a low-jitter clock with <300fs RMS jitter to preserve SNR. Decoupling on each supply pin must use a 0.1uF ceramic placed within 3 mm of the pin. This page synthesizes distributor pricing, drop-in equivalents, and practical design notes not consolidated on the manufacturer datasheet.
LTC2122IUK - Dual 14-Bit 170Msps ADC w/ JESD204B | ADI
The Analog Devices LTC2122IUK is a dual-channel, simultaneously-sampling 14-bit 170 Msps analog-to-digital converter (ADC) with JESD204B serial outputs, housed in a 48-lead QFN (7x7 mm) package with exposed pad. According to the LTC2122 datasheet, the converter delivers 70 dBFS SNR and 90 dBFS spurious-free dynamic range (SFDR) while supporting 1.25 GHz analog input bandwidth for IF/RF undersampling. The device operates from a 1.7V to 1.9V analog supply and integrates an on-chip clock-duty-cycle stabilizer, reducing external PLL requirements for high-speed communication systems. Each channel features a differential input front-end with 600 MHz full-power bandwidth, supporting wideband signal chains from DC to beyond 200 MHz of input frequency. A pipelined ADC architecture uses a high-speed, multi-stage switched-capacitor structure with digital error correction, allowing the LTC2122 to maintain 14-bit linearity up to 170 Msps. Dual-channel simultaneous sampling eliminates inter-channel skew, critical for MIMO receivers, phased-array radar, and diversity antenna systems. The JESD204B serial interface transports the digitized data using up to 4 lanes with 8b/10b encoding, deterministic latency, and embedded clock recovery, which minimizes board routing complexity compared to LVDS parallel interfaces. An on-chip SYSREF input supports deterministic latency for multi-device synchronization in large-channel-count systems. The LTC2122 targets demanding communications applications including LTE and multi-carrier GSM base-station receivers, software-defined radio, cable infrastructure head-end digitization, and high-density MIMO systems. Its 70 dBFS SNR and 90 dBFS SFDR at 170 Msps enable the receiver to digitize a 60 MHz LTE carrier with margin for adjacent-channel blocker rejection. The 1.25 GHz input bandwidth also supports undersampling of L-band and S-band signals, reducing the number of downconversion stages in the signal chain. The 48-QFN (7x7) exposed-pad package provides a low thermal resistance path, allowing operation across the industrial -40C to +85C temperature range without derating at the rated sample rate. For PCB layout, place 0.1uF and 10nF ceramic decoupling capacitors within 5 mm of each supply pin, with the exposed pad soldered to a continuous ground plane. Route the JESD204B serialized lanes as length-matched 100 ohm differential pairs with controlled 50 ohm single-ended impedance, and keep AC-coupled capacitors within 5 mm of the transmitter pins to meet the JESD204B eye-mask specification.
LTC2123CUK - 14-Bit 250Msps Dual ADC, JESD204B | ADI
The Analog Devices LTC2123CUK is a dual-channel, simultaneous-sampling 14-bit, 250 Msps analog-to-digital converter with JESD204B serial outputs, housed in a 48-pin QFN (7x7 mm) package. It is designed for digitizing high-frequency, wide dynamic range signals and is targeted at demanding communications, radar, and test-and-measurement receivers. According to the Analog Devices LTC2123 datasheet, the converter delivers 70 dBFS SNR and 90 dBFS spurious-free dynamic range (SFDR) with a 1.25 GHz input bandwidth that supports accurate IF under-sampling. A pipelined ADC is a multi-stage converter that uses low-resolution flash sub-ADCs and a digital correction network to digitize an analog signal at very high sample rates while maintaining fine amplitude resolution. Within the broader converter taxonomy, pipelined ADCs sit between high-speed flash ADCs and lower-power successive-approximation ADCs, and they are the most widely used architecture for sampling rates from ~50 Msps to several hundred Msps. The LTC2123CUK belongs to this high-speed pipelined class and is positioned for multi-lane serial-data transport via the JEDEC-standardized JESD204B serial interface. Key features include a 14-bit resolution with 250 Msps sample rate, dual simultaneously-sampling analog inputs, an integrated clock and sample-and-hold front end, a 1.25 GHz analog input bandwidth, and a JESD204B-encoded serial data interface that minimizes board-routing complexity. The device operates from standard 1.8 V supply rails and includes internal dithering to improve low-amplitude linearity for small-signal RF work. The LTC2123CUK architecture uses a multi-stage switched-capacitor pipeline with proprietary calibration that flattens the noise and linearity curves across the Nyquist band. By running at 250 Msps from a single 1.8 V supply, the part achieves an SNR floor (70 dBFS) and SFDR (90 dBFS) that previously required dual-supply 5 V parts. The JESD204B Subclass 1 output supports deterministic latency and up to 4 lanes, which simplifies FPGA/ASIC capture when multiple converters must be phase-coherent. Typical applications include multi-antenna diversity receivers, IF digitizers for wireless base stations, broadband instrumentation, phased-array radar signal chains, and high-speed data acquisition test systems. The wide input bandwidth allows straightforward sampling of intermediate frequencies in the second or third Nyquist zone. When designing with the LTC2123CUK, plan the PCB layout for 50 ohm controlled-impedance analog inputs and tightly decouple the two 1.8 V supply domains (analog AVDD and digital DVDD/DRVDD) close to the package. The exposed thermal pad must be soldered to a continuous ground island to keep junction temperature within the commercial 0 to 70 C operating range. This page synthesizes distributor pricing, drop-in compatible variants from the same LTC2123 family, application context, and practical design notes not collected in any single manufacturer document.
LTC2123IUK - 14-Bit 250Msps Dual ADC w/ JESD204B | ADI
The Analog Devices (formerly Linear Technology) LTC2123IUK is a dual 14-bit, 250 Msps analog-to-digital converter with JESD204B serial outputs, housed in a 48-lead QFN (7 mm x 7 mm) package with exposed pad. It is built on a high-performance pipelined architecture and provides two simultaneously-sampling ADC channels on a single die, supporting communications-grade signal chain designs. The listed 1ku price starts at $177.20 per part per the Analog Devices product page. An ADC (Analog-to-Digital Converter) is a mixed-signal data converter IC that samples continuous analog voltages and emits a discrete digital code for downstream processing. High-speed pipelined ADCs are positioned at the top of the converter hierarchy and serve as the gateway between RF/IF analog front-ends and FPGA/DSP digital processing in the signal chain - they are essential for software-defined radio, multi-antenna base stations, and electronic test & measurement instrumentation. Key features of the LTC2123 family include 14-bit resolution, 250 Msps sampling per channel, dual-channel simultaneous sampling, JESD204B serial output protocol for high-speed board-level data transfer, low-jitter clock input, internal dither for spurious-tone improvement, and selectable digital output modes. The 48-QFN package exposes a thermal pad for low-theta-JA board cooling and is qualified for the -40C to +85C industrial temperature range. The pipelined architecture distributes the conversion across cascaded low-resolution stages with redundant bit alignment, achieving high throughput at moderate power per channel while maintaining excellent AC linearity (SFDR, SNR). The integrated JESD204B interface replaces wide parallel LVDS buses with a serialized lane pair, dramatically simplifying FPGA-ADC board routing and improving multi-board synchronization via deterministic latency. Typical applications include LTE/4G/5G base-station receivers, multi-carrier software-defined radio, phased-array radar and EW systems, high-density MIMO digitizers, automated test equipment digitizer cards, and medical imaging front-ends. In all of these, the LTC2123's simultaneous dual-channel 250 Msps operation delivers the per-channel throughput required for direct IF sampling. When designing with this device, allocate a low-noise PLL clock source (e.g., ADF4350/ADF4106), maintain 100-ohm differential input impedance via tight-edad interface, and lay out the JESD204B lanes at length-matched controlled impedance per the JEDEC JESD204B specification to meet the required signal-integrity eye at the receiver. Verify with the manufacturer's evaluation kit (DC2154 or similar) before production.
LTC2140CUP-12 - 12-Bit 25Msps Dual-Channel ADC | Analog Devices
The Analog Devices LTC2140CUP-12 is a 2-channel simultaneous-sampling 12-bit analog-to-digital converter (ADC) designed for digitizing high-frequency, wide-dynamic-range signals, supporting up to 25 Msps per channel in a 64-pin QFN (9 mm x 9 mm) package. It belongs to the LTC2142-12 / LTC2141-12 / LTC2140-12 family, which share a common datasheet and differ primarily in maximum sampling rate (65/40/25 Msps respectively), enabling software-compatible scaling across pipelined ADC designs. An ADC (Analog-to-Digital Converter) is a semiconductor device that samples a continuous analog voltage and converts it to a discrete digital code. In the system hierarchy, an ADC sits between an analog front-end (amplifiers, filters, sensors) and a digital signal processor (DSP, FPGA, or microcontroller). Pipelined ADCs such as the LTC2140CUP-12 use a multi-stage architecture that achieves high sample rates with moderate power consumption by interleaving low-resolution stages, trading slightly higher latency for the ability to capture multi-MHz bandwidth signals at low cost. Key features of the LTC2140CUP-12 include 12-bit resolution, 25 Msps per-channel sample rate, two simultaneously sampled differential or single-ended inputs, a wide input bandwidth, and CMOS or DDR LVDS digital output modes programmable via either a parallel or simple serial interface. The integrated input common-mode buffer and optional digital output randomization further simplify high-performance signal-chain design. Technically, the part uses a multi-stage pipelined architecture with on-chip sample-and-hold, an internal voltage reference, and a digitally programmable gain. The 64-pin QFN package with exposed pad keeps the loop area compact, which is critical at 25 Msps where clock and input edge rates sit near 100 ps. Programmable output modes and configurable full-scale range allow the ADC to interface directly to FPGAs, ASICs, or standard microcontrollers. Typical applications for the LTC2140CUP-12 include wireless base-station receiver IF digitizers, handheld signal analyzers, portable imaging systems, ultrasound front ends, and multi-carrier software-defined radio (SDR) platforms. The combination of low power consumption and dual channels makes it particularly attractive for portable and battery-powered test equipment requiring two synchronized acquisition paths. When designing with this ADC, pay close attention to analog input network layout, decoupling of the internal reference, and the length-matched output routing for DDR LVDS modes. Operating modes are configured through either a parallel CMOS or a simple SPI-style serial interface, allowing all available modes—including output format, gain, and channel selection—to be programmed in-system. This page synthesizes distributor pricing, drop-in alternatives, parameter-by-parameter comparisons, and practical PCB-level design notes not found in the manufacturer datasheet alone.
LTC2140IUP-14 - 14-Bit 25Msps Dual ADC | Analog Devices | 64-QFN
The Analog Devices LTC2140IUP-14 is a 14-bit, 25 Msps low-power dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 64-lead QFN (9x9 mm) package with exposed pad. It integrates two matched ADC channels, each achieving ±1 LSB INL (typical) and ±0.3 LSB DNL (typical) with no missing codes over temperature, plus 1.2 LSBRMS transition noise for clean dynamic range. A pipelined ADC is a high-speed converter architecture that resolves one or two bits per internal stage and combines a sample-and-hold front end with multi-stage switched-capacitor gain/flash blocks; it is the workhorse architecture for communications baseband, ultrasound beamforming, and digital oscilloscope digitizers where multi-Msps rates are required. The LTC2140 sits in the broader hierarchy: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor. Compared with successive-approximation (SAR) ADCs, pipelined parts deliver far higher sample rates at the cost of pipeline latency, while still offering multi-bit-per-stage quantization. Key features include a flexible digital output interface supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS modes, and a separate output supply rail that lets the CMOS swing range from 0.4V to 1.8V independent of the analog 1.8V core. Programmable operating modes are accessible through either a parallel interface or a more flexible serial interface. The two channels sample simultaneously, which is essential for I/Q demodulators, phased-array receivers, and multi-channel data acquisition systems. Typical applications span communications infrastructure (IF/RF digitizers, diversity receivers, multi-antenna baseband), portable and battery-powered imaging, medical ultrasound front ends, industrial inspection cameras, and handheld or bench-top test instrumentation. Two matching channels let the part replace a dual-board ADC+amplifier chain in space-constrained designs. When designing with this part, allocate adequate copper area to the exposed pad for thermal relief (the dual 25 Msps core dissipates non-trivial power at full rate), route the LVDS/CMOS outputs with controlled impedance, and decouple OVDD and AVDD separately. The serial programming interface is recommended when the full feature set (output mode, gain, channel calibration) is required. This page synthesizes distributor stock and pricing, drop-in and same-package alternatives, and practical design notes that are not duplicated on the Analog Devices datasheet.
LTC2141CUP-14 - 14-Bit 40Msps Dual ADC, 64-QFN | Analog Devices
The Analog Devices LTC2141CUP-14 is a 14-bit, 40 Msps low-power dual analog-to-digital converter (ADC) housed in a 64-lead QFN (UP) package measuring 9x9 mm. Each ADC channel features ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over the operating temperature range, and 1.2 LSB RMS transition noise, providing true 14-bit linearity for demanding signal-chain designs. A separate output power supply allows the CMOS output swing to range from 1.2 V to 1.8 V, simplifying interface to modern FPGAs and ASICs. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes at a specified sampling rate. Dual ADCs integrate two synchronized sample-and-hold front ends and two pipelined conversion cores on a single die, enabling simultaneous sampling of two analog channels with matched gain, offset, and aperture delay. They sit within the broader hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. The pipelined architecture used in the LTC2141-14 family balances high sample rate (tens to hundreds of Msps) with low power consumption, making it the dominant choice for communications, imaging, and instrumentation front ends. Key features of the LTC2141CUP-14 include a choice of full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS digital outputs for trade-offs between pin count, board area, and EMI immunity. The device supports both differential and single-ended analog inputs, accepts parallel or serial programming through a simple SPI-like interface, and operates from a single 1.8 V supply. Low power consumption and excellent AC performance (high SNR and SFDR) make it equally suitable for portable, multi-channel data acquisition systems and for dense baseband capture in communications infrastructure. Typical applications include multi-channel communications receivers, portable and battery-powered instrumentation, medical imaging front ends, radar signal processing, and general-purpose high-speed data acquisition. When designing with this part, observe the recommended input common-mode voltage and drive the analog inputs through a wideband transformer or low-noise op-amp driver to preserve SFDR; insufficient analog input bandwidth is the most common root cause of degraded ENOB in pipelined ADC designs.
LTC2141IUP-12 - 12-Bit 40Msps Dual ADC | Analog Devices | 64-QFN
The Analog Devices LTC2141IUP-12 is a 12-bit, 40 Msps, low-power dual-channel pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) exposed-pad package with an industrial -40C to +85C operating temperature range (the "IUP" suffix designates industrial grade). Each of its two simultaneously sampling ADCs features a 12-bit resolution and is designed to digitize high-frequency, wide-dynamic-range signals with excellent spurious-free dynamic range. The device accepts differential or single-ended analog inputs and includes internal references plus an option for an external reference, allowing designers to trade off input range, noise and DC accuracy per channel. According to the manufacturer product page, the LTC2141-12 family lists at a 1ku starting price of $18.78 per part. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed successive-approximation architecture that digitizes analog signals by dividing the conversion into multiple low-resolution stages, each driving a flash sub-ADC and a residue that is amplified and passed to the next stage. The pipelined topology sits within the broader hierarchy of data converters (ADC -> Nyquist ADC -> pipelined ADC -> mixed-signal IC) and is the dominant choice for sample rates from roughly 5 Msps to 200 Msps where both high throughput and low power are required - for example in wireless baseband, medical imaging and defense signal-intelligence receivers. Because the LTC2141-12 contains two matched ADCs sharing one clock, it doubles the channel density of a single 64-QFN footprint relative to two discrete single-channel parts. Key features of the LTC2141IUP-12 include 12-bit resolution, 40 Msps sampling rate, two simultaneously sampled differential input channels, selectable internal/external reference, low power dissipation for the speed class, CMOS-compatible outputs, and an exposed thermal pad that provides a low-theta-JA path for the heat generated by the two converters. The pipelined architecture calibrates its sub-ADC inter-stage gain and offset on-chip, eliminating user calibration and reducing time-to-design. The wide input bandwidth supports undersampling of IF signals, which makes the device attractive in communications receivers that digitize an IF directly rather than first down-converting to baseband. Architecturally, the LTC2141IUP-12 uses a multi-stage switched-capacitor pipeline per channel with proprietary linearization that minimizes integral non-linearity (INL) and differential non-linearity (DNL) at the 12-bit level. Each channel integrates its own sample-and-hold, ensuring matched timing between the two ADCs at the same applied clock edge, which is essential for I/Q demodulation and any diversity or beamforming receiver where the phase relationship between channels must be preserved. The 64-QFN (9x9) exposed-pad package also acts as the primary thermal relief path; PCB design must solder the EP to a continuous ground copper pour to achieve the rated thermal performance. Typical applications for the LTC2141IUP-12 include multi-carrier cellular base-station receivers, software-defined radio (SDR) front-ends, portable instrumentation and oscilloscopes, medical ultrasound beamformers, and industrial non-contact measurement. Industrial-grade temperature range and dual-channel density make it a strong fit when board area and power budget are tightly constrained and two matched channels are needed. When designing with the LTC2141IUP-12, place the part on a continuous ground plane with the exposed pad soldered to multiple thermal vias; this gives the lowest junction-to-ambient thermal resistance. Use short, matched-length differential traces for the analog inputs and keep the analog and digital return currents separated to avoid coupling digital switching noise into the analog front end. Decouple each supply pin with a 0.1uF ceramic capacitor placed as close as possible to the pin, with a bulk 10uF ceramic or tantalum capacitor nearby. This page synthesizes distributor pricing, drop-in package-compatible alternatives, and practical design notes not found in the manufacturer datasheet alone.
LTC2142IUP-12 - 12-Bit 65Msps Dual ADC | Analog Devices
The Analog Devices LTC2142IUP-12 is a 12-bit, 65 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, UPF) exposed-pad package. Designed for digitizing high-frequency, wide-dynamic-range signals, the device combines two matched 12-bit ADC cores with on-chip sample-and-hold and a common reference clock to maintain tight inter-channel phase alignment, making it suitable for diversity receivers and I/Q digitizers where channel-to-channel skew would corrupt image rejection. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time analog voltages into discrete digital codes at a defined sample rate. High-speed pipelined ADCs use a cascade of low-resolution stages to achieve the best trade-off between speed, resolution, and power; the LTC2142-12 family operates between 25 Msps and 65 Msps to cover a range of communications and instrumentation bandwidths. The LTC2142IUP-12 sits in the hierarchy: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. Key performance specifications include 70.8 dB SNR, 89 dB spurious-free dynamic range (SFDR), ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), and no missing codes over the industrial temperature range. Transition noise is specified at 0.3 LSB RMS. The output data interface is programmable between full-rate CMOS, double-data-rate CMOS, and double-data-rate LVDS via a parallel or simple SPI-mode serial configuration register. Typical applications include cellular base-station diversity receivers, multi-antenna software-defined radio (SDR) front-ends, medical ultrasound beamformers, and high-speed instrumentation digitizers. The separate output supply (OVDD) lets the CMOS swing range between 1.2 V and 1.8 V, which allows direct connection to low-voltage FPGAs without level shifters. The operating modes of the LTC2142IUP-12 - including output mode, input range, and power-down - are programmed through either a parallel mode-select pin set or the serial interface for finer control. Designers should follow Analog Devices reference layouts for the 9 mm x 9 mm QFN exposed pad to keep the thermal resistance at the published value. When designing with the LTC2142IUP-12, decouple AVDD and OVDD planes separately and route analog inputs as 50 Ω-1 controlled-impedance differential lines terminated at the ADC inputs to preserve the published SNR and SFDR at full input frequency. This page synthesizes distributor pricing across five channels (DigiKey, Mouser, Octopart, Vyrian, and DigChip) together with same-package pin-compatible variants and practical PCB-layout guidance that is not aggregated on any individual distributor listing.
LTC2142IUP-14 - 14-Bit 65Msps Low-Power Dual ADC | ADI
The Analog Devices LTC2142IUP-14 is a 14-bit, 65 Msps low-power dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-lead 9x9 mm QFN package (UP suffix). The part integrates two matched 14-bit ADC cores that sample on the same clock edge, eliminating inter-channel skew in time-interleaved or I/Q signal chains. What is a dual simultaneous-sampling ADC? A dual ADC is a single integrated circuit containing two matched A/D converter channels that sample their analog inputs at the exact same instant, sharing a common clock. Within the broader signal chain hierarchy, the LTC2142IUP-14 sits inside the data-converter (ADC) class, which is itself a sub-category of data-acquisition ICs, mixed-signal semiconductors, and ultimately integrated circuits. Each converter is preceded by an input track-and-hold and feeds a common reference, allowing direct-IF sampling and quadrature demodulation in communications receivers. Key headline parameters include 14-bit resolution, 65 Msps conversion rate per channel, 73.1 dB SNR, 90 dB SFDR, and a low 100 mW per-channel power dissipation. The device accepts single-ended or differential analog inputs with an input range of 1 Vp-p to 2 Vp-p (set by the MODE pin) and operates from a single 1.8 V analog supply. Digital outputs are LVDS-compatible, easing routing to an FPGA or ASIC across a noisy PCB. A flexible parallel or serial programming interface configures output format, gain, and test patterns. Architecturally, the converter uses a multi-stage pipelined core with proprietary linearization techniques that preserve linearity at high input frequencies, with a typical -3 dB analog input bandwidth of 125 MHz that comfortably exceeds the 65 Msps Nyquist requirement. This makes the part well suited to undersampling intermediate-frequency (IF) signals in wireless infrastructure. Typical applications include 3G/4G cellular base-station receivers, communications imaging, portable instrumentation, ultrasound scanners, and multi-channel data-acquisition cards where channel-to-channel phase coherence is mandatory. Designers frequently pair the LTC2142IUP-14 with low-noise LDOs such as the LT1761 and clock-distribution ICs from the AD951x family. When laying out the PCB, place the analog inputs as close to the ADC pins as possible, use a solid ground plane under the package, and route LVDS outputs with controlled 100 ohm differential impedance. The exposed paddle (EP) must be soldered to a low-impedance ground pad to provide both the electrical ground return and the primary thermal path for the 100 mW internal dissipation. This page synthesizes distributor pricing, package-faithful drop-in alternatives, and applied design notes that go beyond the manufacturer datasheet. It is intended as an engineering-grade reference for BOM managers and hardware designers evaluating the LTC2142IUP-14 for new designs or service replacements.
LTC2143CUP-12 - 12-Bit 80Msps Dual ADC | Analog Devices
The Analog Devices LTC2143CUP-12 is a 12-bit, 80 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) in a 64-pin QFN (9x9 mm) package. It operates from a single 1.8 V supply and integrates two matched ADC cores, on-chip reference, and configurable CMOS/LVDS output modes for direct connection to FPGAs and DSPs. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog waveforms into discrete digital codes for processing by microcontrollers, DSPs, or FPGAs. The pipelined ADC architecture — the hypernym hierarchy of which is: ADC -> data converter -> mixed-signal IC -> semiconductor — is the industry-preferred topology for sample rates from ~10 Msps to >500 Msps because it balances high speed, low power, and small die area. Dual-channel simultaneous-sampling ADCs such as the LTC2143-12 are critical for communications, radar, and I/Q demodulation where two related analog signals must be captured at the exact same instant. Key specifications of the LTC2143CUP-12 include: 12-bit resolution, 80 Msps sample rate, 70.1 dB SNR, 88 dB SFDR, ±0.4 LSB INL (typical), 1.8 V analog/digital supply, and selectable full-scale input range of 1 Vp-p or 2 Vp-p. The serial LVDS output interface (DDR LVDS) supports up to 80 Msps with reduced pin count and excellent common-mode noise rejection. Power consumption is approximately 125 mW per channel at full speed, which is class-leading for the 80 Msps / 12-bit category. Architecturally, the LTC2143-12 uses two interleaved 12-bit pipelined cores with a shared bandgap reference, an on-chip sample-and-hold amplifier, and a digital error-correction block. A self-calibration routine on power-up corrects capacitor mismatch and comparator offset, enabling the 88 dB SFDR performance without external calibration. The inputs are designed for differential drive to maximize even-order harmonic rejection; on-chip common-mode voltage generation simplifies AC-coupling with most modern op-amp drivers. Typical applications for the LTC2143CUP-12 include multi-carrier GSM/EDGE and LTE base-station receivers, diversity radio IF digitization, radar and lidar front-ends, high-speed data acquisition systems, medical imaging (ultrasound beamformers), and communications test equipment. The wide input bandwidth (~750 MHz) also suits the digitizing of IF signals up to ~200 MHz without additional downconversion. When designing with the LTC2143CUP-12, the most important layout consideration is the input network: use a transformer or differential op-amp driver such as the AD8138 with a 25 Ω series resistor at each analog input pin, and place the anti-aliasing RC network as close to the ADC as possible. Decouple the 1.8 V supply with 0.1 µF and 10 µF ceramic capacitors on every supply pin, and keep the LVDS output traces length-matched to within 5 mm to preserve DDR timing margins. This page synthesizes distributor pricing, drop-in same-package alternatives, and design notes that go beyond the manufacturer datasheet — including a parameter-by-parameter comparison table and an explicit selection guide for choosing the LTC2143CUP-12 versus faster or higher-resolution members of the LTC2145-12 / LTC2144-12 / LTC2143-12 family.
LTC2143CUP-14 - 14-Bit 80Msps Dual ADC | Analog Devices
The Analog Devices LTC2143CUP-14 is a 14-bit, 80 Msps, low-power dual pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9) exposed-pad package. The two simultaneously-sampling differential input channels make it well suited for digitizing I/Q baseband, communications IF strips, and multi-channel instrumentation front ends where channel-to-channel phase coherence matters. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and produces a discrete digital code representing its amplitude. Pipelined ADCs achieve a favorable trade-off between sample rate (tens to hundreds of MSPS) and resolution (10-16 bits) by cascading multiple low-resolution stages with inter-stage residue amplification; they are the dominant architecture in communications, imaging, and test-and-measurement front ends. Dual-channel pipelined ADCs such as the LTC2143CUP-14 simultaneously quantize two analog inputs so downstream DSP can recover quadrature relationships, multi-antenna phase, or multi-sensor time correlation. Key specifications include ±1 LSB typical INL, ±0.3 LSB typical DNL with no missing codes over the full temperature range, 1.2 LSB RMS transition noise, and flexible digital outputs supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS. A separate output supply pin lets the CMOS swing range from 1.8 V to 3.3 V independent of the analog 1.8 V core rail, simplifying interface to FPGAs and ASICs on different I/O voltage domains. Typical applications include cellular base-station receivers, software-defined radio (SDR) front ends, multi-channel data acquisition cards, medical ultrasound beamformers, and portable battery-powered instrumentation. The 64-QFN (9x9) exposed pad keeps the package compact while providing a low thermal-resistance path that is essential for the multilayer board ground-plane layout recommended by the manufacturer datasheet. A clean unbroken ground plane in the layer immediately beneath the ADC is required to achieve the published SNR/SFDR performance. A primary design consideration is bypassing the analog and digital rails with low-ESR ceramic capacitors placed within 2 mm of each supply pin and tying the exposed pad to a solid ground pour with at least 16 thermal vias. The internal reference can be disabled in favor of an external reference when tighter gain error or channel matching is required across multiple ADCs.
LTC2143IUP-12 - 12-Bit 80Msps Dual ADC, 64-QFN | Analog Devices
The Analog Devices LTC2143IUP-12 is a 12-bit, 80 Msps, dual-channel, low-power pipelined analog-to-digital converter (ADC) housed in a 64-pin QFN (UP, 9x9 mm) package with exposed pad. The part is specified for the industrial temperature range (-40C to +85C) and operates from a single 1.8 V supply, drawing approximately 100 mW per channel at full sample rate. Per the LTC2145-12/LTC2144-12/LTC2143-12 family datasheet, the device features 70.6 dB SNR and 89 dB spurious-free dynamic range, with simultaneous sampling of two differential analog input channels. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts real-world analog waveforms into discrete digital codes for processing, storage, or transmission. The pipelined ADC architecture — of which the LTC2143IUP-12 is an instance — uses multiple low-resolution stages (typically 1.5 bits/stage) with inter-stage residue amplifiers to achieve high sampling rates at moderate resolution. Pipelined ADCs sit within the broader hierarchy: ADC → data converter → mixed-signal IC → semiconductor. They are the workhorse choice for communications, imaging, and test-and-measurement systems that require multi-MHz input bandwidth and 10-14 bits of resolution. The LTC2143IUP-12 supports input bandwidths up to approximately 750 MHz, allowing it to under-sample IF signals in communications receivers. Internal voltage reference, programmable digital output timing, and flexible LVDS/CMOS output modes simplify board-level integration. The dual, matched channels eliminate skew between ADC paths in MIMO or diversity receivers, while per-channel gain and offset adjustment registers help correct channel-to-channel mismatches at the system level. The 1.8 V single-supply architecture plus low power (about 100 mW per channel at 80 Msps) makes the LTC2143IUP-12 well suited for portable and thermally-constrained instrumentation. Optional LVDS outputs minimize digital switching noise on the board, which is critical when the analog inputs are at the millivolt level. Programmable full-scale input range (1 Vpp or 2 Vpp differential) gives designers headroom when interfacing with a variety of front-end amplifiers and anti-alias filters. Typical applications include cellular base-station receivers, software-defined radio (SDR) platforms, medical imaging front ends, portable test and measurement equipment, and multi-channel data acquisition systems. The wide input bandwidth also suits digital oscilloscopes and spectrum analyzer front ends. When designing with the LTC2143IUP-12, place the analog input traces as 100-ohm differential pairs with a grounded coplanar-waveguide structure, and keep the exposed pad soldered to a continuous ground plane for thermal dissipation and low-impedance return. Use the internal reference by default and decouple AVDD/DVDD/OVRDV with 0.1 uF and 10 uF ceramic capacitors as close to the pins as possible. This page synthesizes DigiKey and Mouser stock/pricing, drop-in pin-compatible alternatives in the same 64-QFN footprint, and practical design notes drawn from the Analog Devices datasheet — information that you will not find on any single distributor page.
LTC2144CUP-14 - 14-Bit 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2144CUP-14 is a 14-bit, 105 Msps dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package with exposed pad, designed for digitizing high-frequency, wide-dynamic-range signals in communications and imaging systems. Key specifications per the Analog Devices datasheet include a 14-bit resolution, 105 Msps sample rate per channel, two synchronized sample-and-hold inputs for simultaneous acquisition, and a low-power CMOS architecture intended for portable and high-density multi-channel designs. What is a simultaneous-sampling ADC? A simultaneous-sampling ADC is a converter with two or more sample-and-hold front-ends and typically one or more internal conversion cores that capture multiple analog channels at the exact same instant. Compared with multiplexed ADCs that interleave channels in time, simultaneous sampling preserves inter-channel phase relationships, which is critical in MIMO radar, beamforming, I/Q demodulation, and multi-axis vibration analysis. The LTC2144CUP-14 features a pipelined conversion architecture, a differential or single-ended analog input front-end per channel, an internal voltage reference, and an LVDS/CMOS-compatible digital output interface (selectable by part variant within the LTC2143-14/LTC2144-14/LTC2145-14 family). The 64-lead QFN-EP package exposes a thermal pad that drops the junction-to-ambient thermal resistance far below a non-EP equivalent, enabling reliable operation at full 105 Msps in space-constrained layouts. Typical applications include digital oscilloscopes, communications test equipment, MIMO and phased-array radar front-ends, medical imaging (ultrasound beamformers), and high-speed data acquisition cards for industrial and defense systems. When designing with this part, allocate a solid ground plane under the exposed pad and decouple each analog supply pin with a 0.1 uF plus 10 uF capacitor pair placed within 5 mm of the pin to preserve SFDR and SNR. This page synthesizes distributor pricing, drop-in alternatives from the LTC2143/LTC2144/LTC2145 family, and practical design notes not found in the manufacturer datasheet alone.
LTC2144IUP-12 - 12-Bit 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2144IUP-12 is a 12-bit, 105 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package with an exposed pad. It is part of the LTC2145-12/LTC2144-12/LTC2143-12 family that delivers 70.6 dB SNR and 89 dB spurious-free dynamic range (SFDR) for digitizing high-frequency, wide dynamic range signals. Ultralow 0.08 ps RMS jitter allows IF undersampling with excellent noise performance. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes. Pipelined ADCs use a multi-stage architecture to achieve high sample rates (tens to hundreds of Msps) while keeping per-stage hardware compact; dual simultaneous-sampling ADCs capture two channels at exactly the same instant, eliminating channel-to-channel skew in I/Q or diversity receivers. Within the power management and data-converter taxonomy, the LTC2144IUP-12 belongs to high-speed pipelined ADCs -> data converters -> mixed-signal ICs -> integrated circuits. Key features of this part include 105 Msps per channel sample rate, 12-bit resolution, 70.6 dB SNR, 89 dB SFDR, 0.08 ps RMS aperture jitter, and a parallel CMOS/LVDS output interface selectable per channel. The 64-QFN (UP) exposed-pad package provides low thermal resistance (~28 C/W theta_JC via the pad), enabling operation across the industrial -40C to +85C temperature range. The pipelined architecture uses 12 internal stages with per-stage flash sub-ADC and MDAC residue amplification; sample-and-hold is on-chip and front-end differential, supporting 1 Vp-p to 2 Vp-p full-scale inputs. A separate output supply (OVDD) lets the digital outputs drive 1.8V to 3.3V logic while the analog core runs from 1.8V. Typical applications include communications receivers, cellular base-station digitizers, radar/sonar signal chains, medical imaging front-ends, and portable test instrumentation. Designers commonly pair it with the AD8138 differential driver at the input and an FPGA for the parallel data capture. Design trade-off: at 105 Msps with 1.8V analog supply, expect roughly 100 mW per channel dissipation. Use the exposed pad with a continuous ground plane and bypass AVDD with 10 uF + 0.1 uF ceramic as close as possible to each pin pair. This page synthesizes distributor pricing, drop-in same-package alternatives, and application-specific design notes not found in the manufacturer datasheet alone.
LTC2144IUP-14 - 14-Bit, 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2144IUP-14 is a 14-bit, 105 Msps low-power dual simultaneous-sampling analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) exposed-pad package. Each of the two integrated channels samples at up to 105 MSPS with pipelined architecture, and the device draws only 312 mW total (approximately 156 mW per channel) from a single 1.8 V supply, with an optional 2.5 V drive for the LVDS/CMOS outputs. What is a dual pipelined ADC? A dual pipelined ADC is an analog-to-digital converter that integrates two independent sample-and-hold front-ends followed by multi-stage switched-capacitor pipeline stages. The architecture enables two channels to be digitized simultaneously, which is critical for applications such as MIMO wireless transceivers, diversity radar, and quadrature (I/Q) signal processing where phase coherence between channels determines system performance. Key features include 73.4 dB SNR and 90 dB SFDR at 70 MHz input, an internal transparent dither circuit that improves SFDR at low input frequencies, and a serial SPI port for mode configuration. The LTC2144-14 family supports CMOS, DDR CMOS, or DDR LVDS output modes, allowing flexible interface to FPGAs and ASICs. A built-in clock duty-cycle stabilizer relaxes PCB clock-routing constraints. The LTC2144IUP-14 is engineered for high-channel-count multi-board systems: a multi-lane serial output mode produces a single-lane serial data stream per channel, reducing FPGA pin count. Internal bandgap reference and proprietary pipeline design eliminate the need for external reference decoupling in most applications, reducing BOM cost. Pin compatibility with the 12-bit LTC2144-12 and 14-bit LTC2143-14 (80 MSPS) variants provides an easy resolution/sample-rate upgrade path within the same QFN-64 footprint. Typical applications include communications basestations (MIMO LTE/WCDMA diversity receivers), handheld portable instrumentation, medical imaging (ultrasound beamforming front-ends), and defense electronics such as phased-array radar digitizers. The industrial temperature range (-40C to +85C) supports outdoor and uncontrolled-environment deployments. When designing with this device, provide a clean low-noise ground plane directly under the exposed pad, route the 105 MHz encode clock as a 50 ohm controlled-impedance trace, and bypass each analog supply pin with a 0.1 uF X7R ceramic capacitor within 3 mm of the pin. The IUP suffix denotes the industrial-grade (-40C to +85C) package. This page synthesizes distributor pricing, drop-in alternatives, and practical layout guidance not found in the bare datasheet, with cross-references to companion Linear Technology ADC families.