LTC2143CUP-14 - 14-Bit 80Msps Dual ADC | Analog Devices
MPN: LTC2143CUP-14 ✓ نشطLTC2143CUP-14 نظرة عامة
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and produces a discrete digital code representing its amplitude. Pipelined ADCs achieve a favorable trade-off between sample rate (tens to hundreds of MSPS) and resolution (10-16 bits) by cascading multiple low-resolution stages with inter-stage residue amplification; they are the dominant architecture in communications, imaging, and test-and-measurement front ends. Dual-channel pipelined ADCs such as the LTC2143CUP-14 simultaneously quantize two analog inputs so downstream DSP can recover quadrature relationships, multi-antenna phase, or multi-sensor time correlation.
Key specifications include ±1 LSB typical INL, ±0.3 LSB typical DNL with no missing codes over the full temperature range, 1.2 LSB RMS transition noise, and flexible digital outputs supporting full-rate CMOS, double-data-rate CMOS, or double-data-rate LVDS. A separate output supply pin lets the CMOS swing range from 1.8 V to 3.3 V independent of the analog 1.8 V core rail, simplifying interface to FPGAs and ASICs on different I/O voltage domains.
Typical applications include cellular base-station receivers, software-defined radio (SDR) front ends, multi-channel data acquisition cards, medical ultrasound beamformers, and portable battery-powered instrumentation. The 64-QFN (9x9) exposed pad keeps the package compact while providing a low thermal-resistance path that is essential for the multilayer board ground-plane layout recommended by the manufacturer datasheet. A clean unbroken ground plane in the layer immediately beneath the ADC is required to achieve the published SNR/SFDR performance.
A primary design consideration is bypassing the analog and digital rails with low-ESR ceramic capacitors placed within 2 mm of each supply pin and tying the exposed pad to a solid ground pour with at least 16 thermal vias. The internal reference can be disabled in favor of an external reference when tighter gain error or channel matching is required across multiple ADCs.
بدائل مباشرة لـ LTC2143CUP-14 — نفس الحزمة، متوافق دبوس بدبوس. تُستثنى القطع ذات الحزم المختلفة التي تتطلب تعديل PCB.
الطرازات في هذه السلسلة
طرازات من نفس السلسلة متوافقة تمامًا مع LTC2143CUP-14 (نفس عامل الشكل والبصمة) — يختلف في Input Type, Package, RoHS Status, Architecture, Number of Channels.
LTC2144CUP-14
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2145CUP-14
✅ بديل مباشر📋 بديل مرجعي (غير موجود في الكتالوج)
LTC2142IUP-14
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2174IUKG-14
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2180IUP
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←ISLA214P25IRZ
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2143CUP-14 الحدود القصوى والخصائص الكهربائية
| الدقة | 14 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 80 MSPS |
| Architecture | Pipelined |
| Input Type | Differential, Single-Ended |
| Data Interface | Parallel CMOS / DDR CMOS / DDR LVDS |
| INL (typical) | ±1 LSB |
| DNL (typical) | ±0.3 LSB |
| Missing Codes | None over temperature |
| Transition Noise | 1.2 LSB RMS |
| Analog Supply Voltage | 1.8 V (typ) |
| Output Supply Voltage | 1.8 V to 3.3 V (separate DVDD supply pin) |
| Reference | Internal or external |
| العلبة | 64-QFN (9x9 mm) with exposed pad (UP) |
| نوع التركيب | Surface Mount |
| درجة حرارة التشغيل | 0 °C to +70 °C (C grade) |
| حالة RoHS | Compliant (#PBF suffix) |
تكوين أطراف LTC2143CUP-14
| دبوس 1 | GND — Ground |
| دبوس 2 | INA+ — Channel A positive differential input |
| دبوس 3 | INA- — Channel A negative differential input |
| دبوس 4 | GND — Ground |
| دبوس 5 | INB+ — Channel B positive differential input |
| دبوس 6 | INB- — Channel B negative differential input |
| دبوس 7 | GND — Ground |
| دبوس 8 | REF — Reference voltage I/O |
| دبوس 9 | REFT — Reference top decoupling |
| دبوس 10 | REFB — Reference bottom decoupling |
| دبوس 11 | MODE — Output mode select (CMOS/DDR CMOS/LVDS) |
| دبوس 12 | GND — Ground |
| دبوس 13 | OVDD — Output driver supply |
| دبوس 14 | D0A — Channel A data output bit 0 (LSB) |
| دبوس 15 | D1A — Channel A data output bit 1 |
| دبوس 16 | D2A — Channel A data output bit 2 |
| دبوس 17 | D3A — Channel A data output bit 3 |
| دبوس 18 | D4A — Channel A data output bit 4 |
| دبوس 19 | D5A — Channel A data output bit 5 |
| دبوس 20 | D6A — Channel A data output bit 6 |
| دبوس 21 | D7A — Channel A data output bit 7 |
| دبوس 22 | D8A — Channel A data output bit 8 |
| دبوس 23 | D9A — Channel A data output bit 9 |
| دبوس 24 | D10A — Channel A data output bit 10 |
| دبوس 25 | D11A — Channel A data output bit 11 |
| دبوس 26 | D12A — Channel A data output bit 12 |
| دبوس 27 | D13A — Channel A data output bit 13 (MSB) |
| دبوس 28 | OGND — Output driver ground |
| دبوس 29 | OVDD — Output driver supply |
| دبوس 30 | D0B — Channel B data output bit 0 (LSB) |
| دبوس 31 | D1B — Channel B data output bit 1 |
| دبوس 32 | D2B — Channel B data output bit 2 |
| دبوس 33 | D3B — Channel B data output bit 3 |
| دبوس 34 | D4B — Channel B data output bit 4 |
| دبوس 35 | D5B — Channel B data output bit 5 |
| دبوس 36 | D6B — Channel B data output bit 6 |
| دبوس 37 | D7B — Channel B data output bit 7 |
| دبوس 38 | D8B — Channel B data output bit 8 |
| دبوس 39 | D9B — Channel B data output bit 9 |
| دبوس 40 | D10B — Channel B data output bit 10 |
| دبوس 41 | D11B — Channel B data output bit 11 |
| دبوس 42 | D12B — Channel B data output bit 12 |
| دبوس 43 | D13B — Channel B data output bit 13 (MSB) |
| دبوس 44 | OGND — Output driver ground |
| دبوس 45 | CLKOUT+ — Differential clock output positive |
| دبوس 46 | CLKOUT- — Differential clock output negative |
| دبوس 47 | OGND — Output driver ground |
| دبوس 48 | OVDD — Output driver supply |
| دبوس 49 | ENC+ — Differential encode clock input positive |
| دبوس 50 | ENC- — Differential encode clock input negative |
| دبوس 51 | CS — Chip select / shutdown control |
| دبوس 52 | GND — Ground |
| دبوس 53 | AVDD — Analog 1.8 V supply |
| دبوس 54 | AVDD — Analog 1.8 V supply |
| دبوس 55 | GND — Ground |
| دبوس 56 | VCM — Common-mode voltage output |
| دبوس 57 | GND — Ground |
| دبوس 58 | SENSE — Reference / ground sense pin |
| دبوس 59 | GND — Ground |
| دبوس 60 | AVDD — Analog 1.8 V supply |
| دبوس 61 | AVDD — Analog 1.8 V supply |
| دبوس 62 | GND — Ground |
| دبوس 63 | AVDD — Analog 1.8 V supply |
| دبوس 64 | AVDD — Analog 1.8 V supply |
التطبيقات النموذجية
LTC2143CUP-14 مناسب لـ 6 التطبيقs: Cellular Base Station Receiver, Software Defined Radio (SDR) Front End, Multi-Channel Data Acquisition Card, Medical Ultrasound Beamformer, Portable Battery-Powered Instrumentation, Radar and Lidar Baseband Digitizer.
Cellular Base Station Receiver
The LTC2143CUP-14's two simultaneously-sampling 14-bit channels at 80 MSPS match the IF bandwidth of multi-carrier GSM/WCDMA/LTE receiver strips where the analog front end downconverts RF to a 70 MHz IF. The 1.2 LSB RMS transition noise and ±0.3 LSB DNL deliver the linearity required for adjacent-channel selectivity, while the LVDS output mode reduces simultaneous-switching noise coupling into the RF chain. Placed after the SAW filter and AGC, the ADC digitizes both polarizations for diversity combining in the baseband DSP.
موصى به
Software Defined Radio (SDR) Front End
The dual-channel architecture of the LTC2143CUP-14 captures I and Q baseband signals with matched gain and phase, which is essential for quadrature demodulation in SDR platforms. At 80 MSPS per channel the device digitizes up to 40 MHz of baseband bandwidth, sufficient for narrowband and many wideband waveforms. The CMOS/DDR/LVDS output flexibility lets the ADC connect directly to FPGAs implementing the digital downconversion and channelization. Differential inputs reject common-mode noise from the RF front end, preserving EVM in dense signal environments.
موصى به
Multi-Channel Data Acquisition Card
Multi-channel PCI/PCIe data acquisition cards use the LTC2143CUP-14 to digitize several analog inputs simultaneously at 80 MSPS, preserving inter-channel timing for vibration, sonar, and acoustic test systems. The 64-QFN exposed-pad package allows dense board layouts with multiple ADCs sharing a clock and reference. Differential inputs reject ground bounce from digital circuitry on the same PCB, while LVDS outputs minimize skew between ADC samples arriving at the FPGA. Synchronization across multiple boards is achieved by sharing the encode clock and the FRAME pulse.
موصى به
Medical Ultrasound Beamformer
Ultrasound systems use arrays of analog front ends feeding high-speed ADCs, where the LTC2143CUP-14's dual simultaneous sampling captures adjacent transducer channels with matched delay. The 14-bit resolution provides sufficient dynamic range for harmonic imaging while keeping power dissipation manageable in portable cart-based systems. LVDS outputs minimize EMI in the sensitive analog front end, and the small 9x9 mm QFN keeps the per-channel board area low for dense array designs. Designers leverage the matched channel-to-channel phase to compute beamformed images in the downstream DSP.
موصى به
Portable Battery-Powered Instrumentation
Handheld oscilloscopes, spectrum analyzers, and field test sets benefit from the LTC2143CUP-14's low power dissipation and dual-channel architecture. The 1.8 V analog supply and separate 1.8-3.3 V output supply allow direct interface to low-power FPGAs without level shifters, reducing total system power. The differential inputs reject switching noise from DC-DC converters that share the battery. The 64-QFN exposed pad provides thermal relief for continuous 80 MSPS operation on a 4-layer FR4 with adequate ground pour.
موصى به
Radar and Lidar Baseband Digitizer
Automotive and industrial radar/lidar baseband receivers use the LTC2143CUP-14 to digitize the I and Q outputs of the mixer at up to 80 MSPS per channel. The matched gain and phase of the two simultaneously-sampled channels preserve the complex-baseband signal structure required for FFT-based range and Doppler processing. The 14-bit resolution captures the dynamic range of chirp signals after LNA and VGA gain, while the LVDS output mode rejects noise on long PCB traces to the processing FPGA. Multiple ADCs can share an external reference for gain-matched multi-receiver arrays.
موصى به
ملخص المنتجات الموصى بها
بيانات مرجعية هندسية لـ LTC2143CUP-14 — المقارنة وإرشادات التصميم ومعلومات الامتثال.
دليل الاختيار
المقارنة مع البدائل
| المعامل | هذا المنتج | LTC2144CUP-14 | LTC2145CUP-14 | LTC2142IUP-14 | LTC2174IUKG-14 | LTC2180IUP |
|---|---|---|---|---|---|---|
| Package | 64-QFN (UP, 9x9 mm) with exposed pad | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UKG) - same family | 64-QFN (UP, 9x9 mm) - same |
| Brand | Analog Devices (formerly Linear Technology) | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 16 bit |
| Sample Rate (per channel) | 80 MSPS | 105 MSPS | 125 MSPS | 65 MSPS | 105 MSPS | 105 MSPS |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Operating Temperature | 0 °C to +70 °C (C grade) | 0 °C to +70 °C | 0 °C to +70 °C | -40 °C to +85 °C (I grade) | -40 °C to +85 °C (I grade) | -40 °C to +85 °C (I grade) |
| Output Modes | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS | CMOS / DDR CMOS / DDR LVDS |
أبرز الفروقات
- Mid-tier sample rate within same-family pin-compatible family (مقابلLTC2145CUP-14)
- Pin-compatible upgrade for higher bandwidth (مقابلLTC2144CUP-14)
- Commercial vs industrial grade option (مقابلLTC2142IUP-14)
ملاحظات التصميم
The LTC2143CUP-14 requires a multilayer PCB with a clean unbroken ground plane in the layer immediately beneath the ADC per the manufacturer datasheet. The exposed pad (pin 65) must be soldered to a ground pour with at least 16 thermal vias (0.3 mm hole, 0.6 mm pitch) to achieve the published thermal resistance and SNR. Low-ESR ceramic bypass capacitors (10 µF + 0.1 µF) must be placed within 2 mm of each AVDD and OVDD pin, with the 0.1 µF cap closest to the pin. Differential input traces should be length-matched within 0.5 mm to preserve inter-channel phase.
Estimated: at 80 MSPS continuous operation with both channels active and 1.8 V analog supply, the LTC2143CUP-14 dissipates roughly 100-130 mW (input values used: typical analog supply current from datasheet family). Forcing the unused channel clock divider or leaving channel B enabled when only A is needed wastes ~10% of total power. The MODE pin selects output mode (CMOS, DDR CMOS, DDR LVDS) and must be configured before reset release; leaving it floating at startup may place the outputs in an indeterminate state. Always provide an explicit logic level on CS and MODE during power-up.
Use the LVDS output mode whenever routing distance to the receiving FPGA exceeds 5 cm; CMOS edges at 80 MSPS generate switching noise that couples back into the analog inputs through the package and PCB. When CMOS mode is unavoidable, series-terminate each output with a 33 Ω resistor placed within 1 cm of the ADC pin to dampen reflections. The ENC+ and ENC- encode pins are differential inputs and should be AC-coupled or DC-coupled from a low-jitter clock source such as the AD9516; phase noise on the encode clock directly translates to aperture jitter and degrades SNR.
معلومات الامتثال
RoHS compliant per #PBF suffix. Not AEC-Q100 qualified; for automotive see ADI's automotive-grade converter portfolio. Operating temperature 0 °C to +70 °C (C grade); I grade variant (LTC2143IUP-14) extends to -40 °C to +85 °C.
