ADC/DAC
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LTC2264CUJ-14 - 14-Bit 40Msps Dual ADC, Serial LVDS, 40-QFN | ADI
The Analog Devices LTC2264CUJ-14 is a 14-bit, 40 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 40-lead QFN (6x6 mm) package with an exposed thermal pad. It provides two simultaneous 14-bit conversions at 40 Msps per channel with serial LVDS digital outputs, and operates from a single 1.8 V supply. The serial LVDS interface minimizes data-line count and eases board routing in multi-channel systems. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed ADC architecture that uses multiple cascaded low-resolution stages to digitize a continuous analog signal, with each stage resolving a portion of the input code while subsequent stages refine the result. Pipelined ADCs occupy the middle ground between flash converters (fastest, lowest resolution) and successive-approximation ADCs (slowest, highest resolution), making them ideal for communications, instrumentation, and imaging applications requiring 10-16 bits at 20-250 Msps. The LTC2264-14 family belongs to the higher-level hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. Key features of the LTC2264CUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and a low 1.2 LSB RMS transition noise. The digital interface can be configured for either 1-lane (one bit per channel) or 2-lane (two bits per channel) LVDS output. The flexible serial or parallel programming interface supports shutdown and nap modes, output format selection, channel selection, and bit-orientation control. The LTC2264-14 architecture combines a low-jitter differential sample-and-hold front end with a multi-stage switched-capacitor pipeline, achieving excellent AC performance (73.1 dB SNR, 88 dB SFDR typical at 4.9 MHz input) while consuming only 69 mW per channel. The part is part of a pin-compatible family with the 65 Msps LTC2265-14 and the 25 Msps LTC2263-14, enabling a single PCB design to support multiple speed grades. Typical applications include communications receivers, cell base stations, digital predistortion feedback paths, handheld signal analyzers, medical imaging front ends, and non-destructive ultrasonic testing. The low power dissipation (138 mW total) and small QFN package make it well suited to portable and densely populated multi-channel systems. When designing with the LTC2264CUJ-14, drive each analog input with a low-jitter differential amplifier to preserve SNR, and route the serial LVDS pairs with controlled 100 Ω differential impedance. The exposed pad must be soldered to a low-impedance ground plane for thermal and electrical performance. Decouple all four supply pins with 0.1 µF and 10 µF capacitors placed as close to the IC as possible. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2264IUJ-12 - 12-Bit 40Msps Dual ADC, 40-QFN | ADI
The Analog Devices LTC2264IUJ-12 is a 12-bit, 40 Msps, dual-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 40-lead QFN (6 mm × 6 mm) package with an exposed pad. It integrates two ADC channels that sample in lock-step, supports analog inputs up to 2 Vp-p, and serial LVDS digital outputs in either 1-lane or 2-lane mode to minimize data-line count. According to the ADI datasheet, the converter achieves ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), and 0.3 LSB RMS transition noise with no missing codes over temperature. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous-time continuous-amplitude analog signals into discrete-time discrete-amplitude digital words. The pipelined ADC architecture employed in the LTC2264-12 family uses multiple low-resolution stages to digitize a sample at high speed with low latency, making it the workhorse of communications, instrumentation, and imaging front-ends. Within the broader taxonomy, this part is a successive-stage pipelined ADC > SAR/pipelined hybrid > data converter > mixed-signal IC > semiconductor. Key features include 73.4 dB SNR and 90 dB SFDR at the Nyquist input frequency, a wide 140 MHz full-power bandwidth, low power dissipation, and an external reference for full-scale range programming. The 40-QFN package with exposed thermal pad provides a low θJA path for high-density multi-channel layouts. Per the ADI datasheet, the part supports both CMOS and LVDS output modes and is offered in commercial (LTC2264C) and industrial (LTC2264I) temperature grades; the LTC2264IUJ-12 is the industrial-temperature 40-QFN variant. The part fits applications such as baseband I/Q digitization in software-defined radio, multi-channel data acquisition in industrial imaging, ultrasound beamformer front-ends, and portable or battery-powered instrumentation where simultaneous-sampling dual channels at moderate sample rates are required. Its serial LVDS interface simplifies board routing and reduces digital switching noise coupling into the analog inputs. A critical design consideration is that LVDS outputs require a 100 Ω differential termination at the receiver and that the analog input common-mode voltage be set within the part's specified range; mis-terminated LVDS lines will degrade SNR and SFDR. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2264IUJ-14 - 14-Bit 40Msps Dual ADC | Analog Devices | Industrial
The Analog Devices LTC2264IUJ-14 is a 14-bit, 40 Msps low-power dual-channel pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6mm x 6mm) package. The LTC2264 family is offered in three speed grades — 25 Msps, 40 Msps, and 65 Msps — with the "-14" suffix denoting the 14-bit resolution and the "40 Msps" speed grade is identified by the part's IUJ-14 marking. The dual-channel architecture integrates two complete ADC channels on a single die, enabling simultaneous sampling for time-interleaved or I/Q signal chain applications. A pipelined ADC (also called a pipeline converter) is a multi-stage successive-approximation architecture that resolves one or two bits per clock cycle across cascaded gain stages. The pipelined topology achieves high sample rates at moderate-to-high resolution with low latency relative to delta-sigma converters and far better dynamic range than flash ADCs at this resolution. Pipelined ADCs sit in the broader data-converter hierarchy: ADC -> Nyquist-rate ADC -> pipelined ADC -> mixed-signal IC -> semiconductor. Within Analog Devices' portfolio, the LTC226x family occupies the low-power, dual-channel pipelined segment. Key specifications of the LTC2264IUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), and guaranteed no missing codes over the full industrial temperature range. Transition noise is specified at 1.2 LSB RMS, contributing to a clean spurious-free dynamic range. The digital outputs use a serial LVDS interface, which minimizes the number of board traces required between the ADC and the downstream FPGA or ASIC. Each channel can be configured to output two bits per clock (2-lane mode) for higher throughput or one bit per clock (1-lane mode) for lower pin-count routing. The part operates from a single 1.8V analog supply and is configured through a serial SPI port. Auxiliary features include shutdown and nap power-down modes, an 800 MHz full-power sample-and-hold bandwidth, and pin compatibility across the 14-bit and 12-bit family members (LTC2264-14/LTC2264-12/LTC2265-14). The pin-compatible 12-bit and 14-bit options allow board-level reuse when the application can trade resolution for SNR. Typical applications include diversity radio receivers, I/Q baseband digitizers, medical imaging front-ends, multi-channel data acquisition systems, and communications test equipment. The dual-channel matched-pair architecture is well-suited to phased-array antenna systems and any signal chain that requires coherent dual-channel sampling. When designing with the LTC2264IUJ-14, pay careful attention to the analog input network: the ADC's S/H front-end benefits from a wideband transformer or differential driver, and LVDS traces must be length-matched and routed with controlled 100-ohm differential impedance. Using the SPI port to enable the nap mode between acquisition bursts can reduce power consumption significantly in duty-cycled applications. This page consolidates distributor pricing, pin-compatible alternatives from the same LTC226x family, and practical design notes that complement (rather than duplicate) the official Analog Devices datasheet.
LTC2265CUJ-12 - 12-Bit 65Msps Dual ADC | Analog Devices
The Analog Devices LTC2265CUJ-12 is a 12-bit, 65Msps low-power dual analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) package with exposed pad. It integrates two simultaneously-sampling 12-bit pipelined ADC cores, accepts 2 differential or single-ended analog inputs, and is specified for 65 Msps per channel, making it suitable for digitizing high-frequency wide-dynamic-range signals in communications and instrumentation. An analog-to-digital converter (ADC) is a semiconductor device that converts continuous analog signals into discrete digital codes. The pipelined ADC architecture, used by the LTC2265CUJ-12, employs multiple cascaded low-resolution stages with sample-and-hold amplifiers and digital error correction. This architecture sits within the broader hierarchy of: ADC -> data converter -> mixed-signal IC -> power management and signal chain semiconductor. Pipelined ADCs are favored over successive-approximation (SAR) types at sample rates above ~10 Msps because they balance speed, resolution and power consumption. Key features of the LTC2265CUJ-12 include dual 12-bit simultaneous-sampling channels at 65 Msps each, low power consumption, an LVDS or CMOS selectable digital interface, integrated input buffers and a flexible clock input. The 40-lead QFN (6x6) package provides a small footprint while the exposed thermal pad ensures low thermal resistance (theta-JA approximately 30 C/W) suitable for fanless embedded designs. Per the manufacturer datasheet, the part supports an analog supply near 1.8V and a digital supply near 1.8V, both essential for low-power operation. The LTC2265CUJ-12 uses a multi-stage pipeline per channel with proprietary SHA front-end and on-chip dither, achieving effective spurious-free dynamic range (SFDR) well above Nyquist with no missing codes. The dual simultaneous sampling enables I/Q demodulation or orthogonal channel capture without external synchronization, a distinct advantage over multiplexed ADCs. Typical applications include cellular base-station receivers, IF sampling in software-defined radio, medical imaging front-ends such as ultrasound, multi-channel data acquisition and industrial process control. Designers commonly pair the ADC with an Analog Devices low-noise LDO such as the LT3042 and a high-speed differential amplifier such as the ADA4927 to realize a complete signal chain. When designing with this device, maintain a continuous clock at the ENC input, decouple AVDD and DVDD with 1uF and 0.1uF ceramic capacitors placed within 2mm of the supply pins, and provide a clean low-jitter clock. Input common-mode and input amplitude must conform to the datasheet's recommended settings to preserve SFDR. This page synthesizes distributor pricing, drop-in same-package alternatives and practical design notes not found in the manufacturer datasheet alone, helping engineers shorten selection and qualification cycles.
LTC2265CUJ-14 - 14-Bit 65Msps Dual ADC | Analog Devices
The Analog Devices LTC2265CUJ-14 is a 14-bit, dual-channel, 65 Msps (mega-samples per second) low-power pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) package. It delivers ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and 1.2 LSB RMS transition noise. The digital outputs are serial LVDS, supporting both 1-lane and 2-lane modes to minimize the number of data lines. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that converts continuous analog voltage signals into discrete digital codes. Pipelined ADCs use a multi-stage architecture that delivers high sample rates (>10 Msps) at moderate resolution (10-16 bits) with low power consumption, making them ideal for digitizing high-frequency, wide-dynamic-range signals in communications, instrumentation, and imaging applications. Key features of the LTC2265CUJ-14 include an 800 MHz full-power sample-and-hold bandwidth, shutdown and nap modes for power saving, and a serial SPI port for configuration. Its pin-compatible 14-bit/12-bit family (LTC2265-14, LTC2264-14, LTC2263-14) and 40-pin 6x6 mm QFN footprint enable drop-in scalability across sample rates and resolutions. The device operates from a 1.8 V analog/digital supply (VDD = OVDD = 1.8 V), drawing low power suitable for portable and multi-channel systems. The differential input architecture and LVDS outputs minimize digital noise coupling, supporting direct connection to FPGAs and DSPs in high-speed signal chains. Typical applications include communications receivers, basestation digitizers, software-defined radio (SDR), portable instrumentation, and multi-channel data acquisition systems. The wide input bandwidth also supports IF (intermediate frequency) sampling in radar and medical imaging front ends. When designing with the LTC2265CUJ-14, use a low-jitter clock at ENC+/ENC- and place input anti-aliasing capacitors close to the analog inputs. The LVDS output format requires 100-ohm differential termination at the receiver. The SPI port enables dynamic mode selection between 1-lane and 2-lane output and shutdown control for power sequencing. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes that go beyond the manufacturer datasheet, giving engineers a single reference for selection, sourcing, and PCB layout planning.
LTC2265IUJ-14 - 14-Bit 65Msps Dual ADC, 40-QFN | Analog Devices
The Analog Devices LTC2265IUJ-14 is a 14-bit, 65 Msps, low-power dual-channel pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) package with an exposed pad (HVQCCN, no-lead). The 'IUJ' suffix denotes the industrial temperature grade (-40C to +85C), the '14' indicates 14-bit resolution, and the device integrates two simultaneously-sampling ADC channels ideal for communications, IF-signal capture, and multi-channel data acquisition. A pipelined ADC is a high-speed converter architecture that uses multiple cascaded low-resolution flash stages to digitize an analog signal at sample rates far higher than successive-approximation designs. The LTC2265IUJ-14 sits within the broader hierarchy: ADC -> data converter -> signal chain IC -> semiconductor. It uses serial LVDS digital outputs to minimize the number of data lines on the PCB, supporting both 2-lane (two bits per channel per clock) and 1-lane (one bit per channel per clock) modes. Key features include DC specifications of typical 1LSB INL, typical 0.3LSB DNL, no missing codes over temperature, and a low 1.2 LSB RMS transition noise. The serial LVDS interface reduces pin count, easing PCB routing in dense multi-channel systems. Each channel can be independently enabled, allowing power saving in single-channel applications. Typical applications include cellular base-station IF digitizers, software-defined radios, multichannel industrial instrumentation, medical imaging front ends, and any system that requires two simultaneously-sampled analog channels at moderate sample rates. The 40-QFN exposed pad provides a low thermal resistance path to the PCB. When designing with this part, allocate adequate PCB copper area beneath the exposed pad for thermal dissipation. The serial LVDS outputs require careful PCB impedance control (typically 100 ohm differential) and matched trace lengths to maintain data valid timing.
LTC2266CUJ-12 - 12-Bit 80Msps Dual ADC, 40-QFN | Analog Devices
The Analog Devices LTC2266CUJ-12 is a 12-bit, 80 Msps low-power dual-channel pipelined analog-to-digital converter (ADC) housed in a 40-pin QFN (6mm x 6mm) package. It integrates two simultaneously-sampling ADCs with a single shared clock, supports selectable input ranges from 1 Vp-p to 2 Vp-p, and provides 800 MHz full-power input bandwidth. The part is specified over the commercial 0C to +70C temperature range, and the LTC2266IUJ-12 industrial-grade variant is pin-compatible for -40C to +85C applications. An ADC (analog-to-digital converter) is a data converter integrated circuit that translates continuous analog voltage levels into discrete digital codes, sitting at the boundary between the analog signal chain and the digital processing domain. Within the broader semiconductor taxonomy, the LTC2266CUJ-12 is a successive-approximation/pipelined ADC -> ADC -> data converter IC -> integrated circuit. Pipelined ADCs are the dominant architecture for sampling rates from ~10 Msps to several hundred Msps, offering the best trade-off between speed, resolution, and power dissipation for communications, imaging, and test-and-measurement front ends. Key features of the LTC2266CUJ-12 include 12-bit resolution, 80 Msps sample rate, two matched ADC channels, 800 MHz full-power bandwidth, low power dissipation, SPI-port configurable modes, shutdown and nap power-down modes, and pin compatibility with the 14-bit LTC2266-14 and LTC2261-14 family. The dual-channel integration halves board area versus two discrete single-channel ADCs and eliminates the channel-to-channel skew inherent in time-interleaved solutions. The pipelined architecture uses multi-bit/stage gain stages with digital error correction, delivering excellent spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) while keeping per-channel power below 100 mW typical. Internal references and a low-jitter clock buffer reduce external component count, and the SPI port allows runtime configuration of input range, output data format, and power modes. Typical applications include communications baseband and IF digitizers, medical imaging receivers, portable and battery-powered test equipment, multi-channel data acquisition systems, and diversity radio receivers. The dual channel also makes it well-suited to I/Q demodulation in direct-conversion receivers. When designing with the LTC2266CUJ-12, pay attention to analog input drive network (transformer or active driver), low-jitter clock source, and decoupling at each supply pin. The exposed pad (EP) must be soldered to a continuous ground plane to meet the rated thermal performance; the SPI pins are 1.8V-3.3V logic and require level shifting on hosts that run above 3.3V. This page synthesizes Analog Devices datasheet specifications, distributor pricing tiers, drop-in compatible alternatives, and PCB design notes not bundled in the manufacturer datasheet. All values are anchored to distributor data as of 2026-10-13.
LTC2266CUJ-14 - 14-Bit 80Msps Dual ADC | Analog Devices | 40-QFN
The Analog Devices LTC2266CUJ-14 is a 14-bit, 80Msps, low-power dual analog-to-digital converter (ADC) housed in a 40-pin QFN (6mm x 6mm) package. The part features two simultaneously-sampling ADC channels with pipelined architecture, ±1LSB (typ) INL and ±0.3LSB (typ) DNL, guaranteed no missing codes over temperature, and 1.2LSB RMS transition noise. Each channel provides serial LVDS digital outputs that minimize data-line count, with selectable 2-lane (2 bits per channel per clock) or 1-lane (1 bit per channel per clock) output modes for flexible FPGA/ASIC interfacing. What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed data-conversion architecture that uses multiple cascaded low-resolution flash stages to convert analog samples to a digital code in successive clock cycles. Pipelined ADCs sit inside the broader ADC family (which also includes SAR, delta-sigma, and flash), and they are the architecture of choice for sample rates from ~10Msps to several hundred Msps because they balance conversion speed, resolution (typically 8-16 bits), and dynamic power. The dual-channel LTE2266 provides two independent ADC cores on a single die, simplifying multi-channel communication, radar, and instrumentation designs that need synchronized sampling. Key features of the LTC2266CUJ-14 include an 800MHz full-power sample-and-hold bandwidth, shutdown and nap power-save modes, an SPI serial port for mode configuration, and pin compatibility with 12-bit (LTC2266-12) and faster 14-bit (LTC2267-14 at 105Msps, LTC2268-14 at 125Msps) variants. The 40-pin QFN package integrates a thermally-enhanced exposed pad for low thermal resistance, which combined with the part's 1.8V analog supply operation keeps total power dissipation low enough for compact multi-channel systems. At the architecture level, the LTC2266-14 uses a multi-stage differential pipeline with on-chip reference and sample-and-hold, internal bandgap-derived voltage reference, and selectable digital output serialization that lets the user trade off pin count for channel throughput. Typical applications for the LTC2266CUJ-14 include communications infrastructure such as cellular base-station receivers and software-defined radio (SDR) front-ends, dual-channel test and measurement equipment, simultaneous-sampling data-acquisition systems, and multi-antenna diversity receivers. The low-power operation makes it equally suitable for portable instrumentation. When designing with this part, ensure that the analog inputs are AC-coupled or DC-biased within the input common-mode range, and provide solid ground stitching and decoupling around the exposed pad to achieve the rated SNR. Pin compatibility with the LTC2267-14 and LTC2268-14 in the same 40-QFN package allows one PCB layout to serve multiple speed grades. This page synthesizes distributor pricing, recommended pin-compatible drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2266IUJ-12 - 12-Bit 80Msps Dual ADC | Analog Devices
The Analog Devices LTC2266IUJ-12 is a 12-bit, 80 Msps dual-channel low-power pipelined analog-to-digital converter housed in a 40-pin QFN (6 mm x 6 mm) package. The part provides two simultaneously-sampling ADC channels with selectable input ranges of 1 Vp-p to 2 Vp-p, an 800 MHz full-power bandwidth sample-and-hold front end, and serial SPI configuration of operating modes. The industrial-grade "I" temperature grade supports the -40C to +85C ambient range. The 6 mm x 6 mm QFN footprint integrates both channels on a single die, simplifying PCB routing for multi-channel data capture systems. A pipelined ADC is a high-speed analog-to-digital converter architecture that resolves one or two bits per clock stage across multiple cascaded gain stages, achieving tens to hundreds of MSps while keeping per-stage power dissipation modest. Pipelined ADCs sit in the broader hierarchy of Nyquist-rate data converters (SAR, pipeline, flash), and are widely used in communications infrastructure, digital oscilloscopes, and imaging systems where sample rate matters more than absolute DC precision. The LTC2266-12 belongs to Analog Devices' LTC2266 family of dual ADCs, which shares pinout with the 14-bit LTC2266-14 and 10-bit LTC2266-10 versions, enabling a single PCB layout to support multiple resolution points. Key features include 64.9 dB SNR (typical), 80 dB SFDR, an internal reference, shutdown and nap power-down modes for energy-conscious designs, and a flexible LVDS or CMOS output interface selectable through the SPI port. The integrated bypass-and-decoupling network lets the part operate from a single 1.8 V analog supply, simplifying board design compared to discrete ADC plus driver arrangements. Architecturally, each channel uses a multi-stage switched-capacitor pipeline fronted by a wideband track-and-hold, followed by digital error correction. The dual ADC architecture allows I/Q capture in direct-conversion receivers or simultaneous sampling of two sensor channels in instrumentation. Typical applications include software-defined radio receivers, medical imaging front-ends, multi-channel data acquisition modules, communications baseband digitizers, and handheld oscilloscope or spectrum analyzer probes. When designing with this device, pay attention to LVDS/CMOS output termination and decoupling close to the supply pins; for demanding spurious performance, use the internal dither mode enabled via SPI.
LTC2267CUJ-12 - 12-Bit 105Msps Dual ADC, Low Power | ADI
The Analog Devices LTC2267CUJ-12 is a 12-bit, 105 Msps low-power dual analog-to-digital converter (ADC) housed in a 40-pin QFN (6x6 mm) package. The part delivers two simultaneously-sampling pipelined ADC channels from a single 1.8 V analog supply, with serial LVDS digital outputs and pin-selectable 1-lane or 2-lane output mode per channel. Typical DC linearity is ±0.3 LSB INL and ±0.1 LSB DNL with no missing codes over the full operating temperature range. A dual pipelined ADC is a member of the high-speed converter family in the data-converter hierarchy, which itself sits inside the broader mixed-signal IC category of power management and signal-conditioning devices. Within that hierarchy, a pipelined ADC is the de-facto choice for sample rates between roughly 1 Msps and 500 Msps because it offers an excellent trade-off between speed, resolution, and silicon area; the dual-channel variant extends this to multi-antenna, I/Q, or diversity receiver systems where two coherent conversions are needed from the same clock. Key features of the LTC2267CUJ-12 include low 0.3 LSB RMS transition noise, serial LVDS outputs that minimize data-line count, internal bypassed reference, and a flexible clock duty-cycle stabilizer. The integrated 2-lane output mode reduces the FPGA pin count while still delivering both bits of each conversion in parallel; the 1-lane mode further reduces routing complexity at lower sample rates. A SPI-compatible serial interface allows per-channel gain, offset, and phase trim for channel matching. The device is specified over the commercial 0 °C to +70 °C operating range with the LTC2267IUJ-12 industrial-grade variant covering -40 °C to +85 °C. The 40-pin QFN (6x6 mm) package exposes the die ground paddle on the bottom for low-impedance grounding and thermal relief, and is pin-compatible with the broader LTC226x-12/14 family of 12-/14-bit dual ADCs from Analog Devices. Typical applications include multi-antenna wireless receivers, software-defined radio (SDR) front-ends, I/Q baseband digitization, low-power portable instrumentation, medical imaging receive channels, and LTE/3G diversity radio paths. Designers often pair the LTC2267CUJ-12 with an LT6203 or ADA4937 driver in front and an FPGA such as a Xilinx Spartan-6 or Altera Cyclone IV on the LVDS side. A key design consideration is LVDS trace length matching: the two bits of each conversion must be deskewed by the receiver, so pairs should be routed with controlled impedance (100 Ω differential) and matched to within roughly 100 mil. The exposed pad must be soldered to a continuous ground plane for both electrical and thermal reasons; bypassing the 1.8 V analog supply with 10 µF bulk plus 0.1 µF ceramic at every pin is essential to meet the noise floor at 105 Msps. This page synthesizes distributor stock, drop-in compatible pin-compatible LTC226x family members, and practical LVDS-layout design guidance not found in the manufacturer datasheet.
LTC2267CUJ-14 - 14-Bit 105Msps Dual ADC, Serial LVDS | ADI
The Analog Devices LTC2267CUJ-14 is a 14-bit, 105 Msps dual-channel pipelined analog-to-digital converter (ADC) with serial LVDS outputs, housed in a 40-pin (6mm × 6mm) QFN package. The part includes two simultaneous sampling ADC channels, each providing 14-bit resolution at up to 105 Msps with 73.4 dB SNR and 85 dB SFDR, making it suitable for communications, instrumentation, and high-speed imaging front-ends. What is a pipelined dual ADC? A pipelined ADC is the dominant converter architecture for sample rates from about 10 Msps to several hundred Msps. It uses multiple low-resolution stages to digitize the input, with each stage driving the next while the previous sample is being held; this parallelism achieves high throughput while keeping per-stage accuracy modest. Dual (2-channel) variants integrate two such pipelines on one die with shared clocking, enabling simultaneous sampling of I/Q or two sensor channels. ADCs are part of the broader data-converter hierarchy: data converter -> ADC -> high-speed ADC -> pipelined ADC. Compared with SAR or sigma-delta types, pipelined ADCs sacrifice latency and per-sample settling in exchange for the highest sustained conversion rates at moderate (10-16 bit) resolution. Key features of the LTC2267CUJ-14 include ±1 LSB INL (typical), ±0.3 LSB DNL (typical), no missing codes over temperature, and 1.2 LSB RMS transition noise. Each channel outputs data over two LVDS lanes (2-lane mode), with a 1-lane option available at lower sampling rates to reduce board routing complexity. Serialization is selectable at 16-, 14-, or 12-bit widths, and the device includes an 800 MHz full-power sample-and-hold amplifier, shutdown and nap power modes, and a serial SPI port for configuration. The architecture is based on a switched-capacitor pipeline with proprietary calibration logic that trims capacitor mismatch at power-up and on demand. The high-bandwidth track-and-hold front-end preserves signal integrity for IF-sampling receivers, while the low-jitter clock-recovery-friendly LVDS interface simplifies FPGA/ASIC interconnect. Per-channel power is approximately 135 mW at 105 Msps, dropping further in nap and shutdown states. Typical applications include cellular base-station receivers, software-defined radio, radar and lidar digitizers, medical imaging, and portable test instrumentation. The wide input bandwidth also enables direct IF sampling, removing a mixer stage in many receiver chains. The device is pin-compatible with the 14-bit and 12-bit versions in Analog Devices' LTC226x family, enabling a single PCB to support multiple resolutions. When designing with the LTC2267CUJ-14, allocate a quiet analog ground plane under the package and route the LVDS pairs as 100-ohm differential microstrip. A low-jitter clock (>100 fs rms jitter) is required to preserve SNR at high input frequencies; follow the datasheet reference decoupling scheme exactly. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical layout notes that go beyond the datasheet.
LTC2267IUJ-14 - 14-Bit 105Msps Dual ADC | Analog Devices
The Analog Devices LTC2267IUJ-14 is a 14-bit, 105Msps dual-channel pipelined analog-to-digital converter (ADC) housed in a 40-pin 6mm × 6mm QFN package. The LTC2267IUJ-14#PBF lead-free variant integrates two simultaneous-sampling ADC channels, each with 1.2 LSB RMS transition noise and ±1 LSB (typ) INL, and offers serial LVDS digital outputs that minimize the number of required data lines. A pipelined ADC is a high-speed successive-approximation architecture in which each conversion stage resolves a few bits and passes the residue to the next stage, enabling 100+ Msps sampling while keeping per-stage gain and bandwidth requirements modest. The LTC2267-14 family targets low-power instrumentation, communications baseband, and diversity-radio IF digitizing where both channels must be captured simultaneously and with deterministic latency. Key features include 105Msps guaranteed sampling rate, ±0.3 LSB (typ) DNL, ±1 LSB (typ) INL with no missing codes over temperature, and 1.2 LSB RMS transition noise. According to the LTC2268-14 / LTC2267-14 / LTC2266-14 datasheet, the parts deliver 800 MHz full-power sample-and-hold bandwidth, configurable 2-lane / 1-lane LVDS output serialization (16-, 14-, or 12-bit), shutdown and nap modes, plus a serial SPI port for configuration. Pin-compatible 14-bit and 12-bit family members (LTC2268-14 / LTC2267-14 / LTC2266-14) simplify system scaling across speed grades. Typical applications include diversity/MIMO receiver IF digitizing, cellular base-station baseband sampling, software-defined radio (SDR), handheld signal analyzers, and low-power multi-channel data acquisition front-ends. The 6mm × 6mm QFN-40 package and SPI control interface support compact, low-power PCB designs. When designing with this part, ensure the analog input drive network presents the correct 50 Ω differential termination to preserve SFDR. Decouple AVDD and DVDD rails independently, and use the shutdown/nap pins for power gating between sample bursts. The LTC2267IUJ-14 is the industrial (-40 °C to +85 °C) temperature grade; the LTC2267CUJ-14 is the commercial variant.
LTC2268IUJ-12 - 12-Bit 125Msps Dual ADC, 40-QFN | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2268IUJ-12 is a 12-bit, 125 Msps dual-channel low-power pipelined analog-to-digital converter (ADC) housed in a 40-lead QFN (6x6 mm) package. It provides two simultaneously-sampling ADC channels with serial LVDS digital outputs, achieving 71 dB SNR and 84 dB SFDR at baseband while consuming only 230 mW per channel from a single 1.8 V supply. The digital output interface operates in either 2-lane (DDR) or 1-lane (SDR) mode to minimize the number of data lines. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog voltage signals into discrete digital codes for processing by FPGAs, ASICs, microcontrollers, or DSPs. Within the converter hierarchy, the LTC2268IUJ-12 sits at the pipelined ADC subclass, which uses multiple low-resolution flash stages to digitize high-speed signals efficiently. As a dual synchronous-sampling ADC it belongs to the data-converter family -> signal-chain IC -> mixed-signal IC -> semiconductor taxonomy. The low-power 1.8 V architecture makes it suitable for portable and thermally-constrained multi-channel systems. Key features include ±0.3 LSB INL (typical), ±0.1 LSB DNL (typical), no missing codes over temperature, and 0.3 LSB RMS transition noise. The analog input is single-ended with an internal bypass reference and accepts differential or single-ended drive, simplifying front-end design. The output data is serialized over LVDS, reducing the FPGA/ASIC pin count to as few as 3 pins per channel. The LTC2268IUJ-12 is part of the broader LTC2268-12 family which provides pin-compatible speed grades (80 Msps / 105 Msps / 125 Msps) for design scalability. Architecturally, the device uses a multi-stage pipelined architecture with digital error correction and an internal high-precision bandgap reference. Each stage produces a sub-ADC result, drives a DAC, and computes a residue for the next stage; final alignment produces the 12-bit code. The serial LVDS interface uses an internal PLL to derive the DDR clock from the input encode clock, eliminating the need for a separate data-clock line at sample rates up to 125 Msps. Typical applications include multi-channel digital oscilloscopes, communications test equipment, software-defined radio (SDR) receivers, medical imaging front ends, and high-speed industrial imaging. The wide input bandwidth supports undersampling of IF/RF signals in communications systems. The LVDS output directly connects to modern FPGAs with built-in LVDS receivers (e.g., Xilinx 7-series, Intel/Altera Cyclone). For multi-board systems, the LTC2268IUJ-12 enables compact synchronized sampling without external delay-matching ICs. When designing with this part, observe the analog input common-mode voltage requirement (0.9 V typical) to maximize SNR; AC-coupling transformers or driver op-amps (e.g., ADA4927, ADL5562) are typically used at the inputs. Provide a low-noise 1.8 V analog supply and a separate 1.8 V digital supply with a ferrite-bead isolation. Synchronize the encode clock with low-jitter sources such as a TCXO or dedicated clock generator; phase noise of the encode clock directly degrades SNR. The QFN-40 package requires thermal vias under the exposed pad to meet the rated performance over -40C to +85C. This page synthesizes distributor pricing, drop-in pin-compatible alternatives across the LTC2268 family and competitor ADCs, and design notes that go beyond the manufacturer datasheet.
LTC2268IUJ-14 - 14-Bit 125Msps Dual ADC, LVDS | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2268IUJ-14 is a 14-bit, 125 Msps, dual-channel, low-power analog-to-digital converter (ADC) housed in a 40-pin QFN (6 mm x 6 mm) package with an exposed pad. It provides two simultaneously sampling pipelined ADC channels with serial LVDS digital outputs, accepts differential analog inputs, and operates from 1.7 V to 1.9 V analog and digital supplies. Typical DC performance is ±1 LSB INL, ±0.3 LSB DNL, and 1.2 LSB RMS transition noise with no missing codes across the industrial temperature range. A pipelined ADC is a high-speed successive-stage converter architecture in which each clock cycle advances the sampled signal through low-resolution flash stages, producing N bits of resolution at sample rates from tens to hundreds of Msps. Pipelined ADCs sit within the broader data-converter hierarchy (ADC -> Nyquist-rate ADC -> high-speed converter -> mixed-signal IC) and are the workhorse of communications, instrumentation, and imaging front ends where multi-channel simultaneity, wide analog bandwidth, and serial LVDS output are required to feed an FPGA or ASIC. Key features include an 800 MHz full-power sample-and-hold bandwidth, 73 dB SNR and 90 dB SFDR at baseband (typical), 2-lane LVDS serialization configurable to 16-, 14-, or 12-bit framing, pin-compatible 14-bit and 12-bit family members, and shutdown plus nap modes for power-sensitive designs. The serial LVDS interface minimizes data-line count and FPGA pin usage, while SPI-port configuration allows flexible output formatting per channel. Typical applications include cellular base-station receivers, diversity radio, test and measurement instrumentation, digital predistortion feedback paths, medical imaging front-ends, and multi-channel data-acquisition cards. Per the manufacturer datasheet, the LTC2268-14 family starts from $79.69 per 1k unit, with the LTC2268IUJ-14#PBF version offered by authorized distributors including DigiKey and Mouser. When designing in this part, observe the differential-input common-mode requirement and place 0.1 µF bypass capacitors as close as possible to each supply pin with a larger bulk capacitor on the analog AVDD rail. The exposed pad must be soldered to a continuous ground plane for thermal dissipation and low-inductance return. LVDS trace length matching and 100 Ω differential termination are critical to preserve signal integrity at 125 Msps. This page synthesizes distributor pricing, pin-compatible family alternatives, and practical PCB-layout guidance not found in the manufacturer datasheet alone.
LTC2270CUP - 16-Bit 20Msps Dual ADC | Analog Devices
The Analog Devices LTC2270CUP is a 16-bit, 20 Msps, low-noise, dual-channel simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package with exposed pad. Each channel delivers 84.1 dB SNR and 99 dBc spurious-free dynamic range (SFDR) at baseband, with a fully differential input that accepts single-ended or differential signals up to 2 Vp-p on each input. The device uses an internal high-precision reference and offers low-jitter clocking with CMOS-compatible digital outputs for direct connection to FPGAs and DSPs. An ADC (analog-to-digital converter) is a semiconductor device that converts real-world analog signals into discrete digital codes for downstream processing by DSPs, FPGAs, or microcontrollers. Within the signal chain hierarchy (sensor -> analog front end -> ADC -> DSP/FPGA -> actuator), the dual-channel 16-bit 20 Msps ADC occupies the bridge between the analog conditioning stage and digital processing. Pipelined ADCs such as the LTC2270CUP are favored for communications, IF-sampling, and instrumentation because they combine high sampling rates with resolutions above 14 bits, while successive-approximation ADCs serve lower-speed precision roles and delta-sigma ADCs serve high-resolution DC/low-bandwidth tasks. Key features of the LTC2270CUP include 84.1 dB SNR and 99 dBc SFDR at 5 MHz input, an internal bandgap reference (or optional external reference), programmable gain from 0.5 dB to 1.5 dB in 0.5 dB steps, and a low-latency digital interface that latches each conversion on a single output clock rising edge. The differential inputs ease board-level EMI rejection, and the QFN-64 EP package offers a thermal resistance that supports full-rate operation across the 0 C to 70 C commercial range without external heatsinking. In terms of architecture, two matched pipelined ADC cores share a single low-jitter clock distribution network and a common reference, ensuring that channel-to-channel gain, offset, and timing mismatches remain below the noise floor. This tracking is essential for diversity receivers, I/Q demodulation, and any system where correlated dual-channel acquisition is required (for example, quadrature sampling of complex baseband signals). The pipelined core provides digital error correction per stage and outputs true 16-bit data with no missing codes at room temperature. Typical applications include cellular base-station diversity receivers, multiband software-defined radio IF strips, instrumentation and test equipment, low-latency digital oscilloscopes, medical imaging front ends, and industrial process control loops. Designers prefer this part when simultaneous sampling on two matched channels simplifies I/Q or diversity capture. The wideband noise floor and linearity also suit direct IF sampling of intermediate-frequency carriers up to several hundred megahertz. When designing with the LTC2270CUP, ensure the input common-mode and coupling network match the recommended application circuit, place decoupling within a few millimeters of each supply pin, and bond the exposed pad to a continuous ground plane for thermal and electrical performance. The 1.5 dB programmable input gain allows trade-offs between noise figure and full-scale headroom for downstream FPGA decimation stages. This page consolidates distributor pricing, drop-in compatible ADCs, recommended decoupling topology, and application guidance not contained in a single manufacturer datasheet - giving system engineers a single reference point for part selection and PCB bring-up.
LTC2270IUP - 16-Bit 20Msps Dual ADC, 84.1dB SNR | Analog Devices
The Analog Devices LTC2270IUP is a 16-bit, 20 Msps, two-channel simultaneous-sampling pipelined analog-to-digital converter housed in a 64-pin QFN (9x9 mm) package, with industrial temperature grade (-40C to +85C). The IUP suffix indicates the QFN-64 package plus the industrial operating range, while the underlying die delivers 84.1 dB SNR and 99 dB spurious-free dynamic range (SFDR) for demanding wide-bandwidth signal chains. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that quantifies continuous-time analog voltages into discrete digital codes, forming the bridge between the analog front end (sensors, filters, amplifiers) and the digital signal processor or FPGA. In the system hierarchy, the LTC2270IUP sits between the analog conditioning stage and the digital processor: signal chain -> data acquisition -> ADC -> DSP/FPGA. Pipelined ADCs like the LTC2270 use a multi-stage architecture to achieve high sampling rates (tens of Msps) while preserving 14-16 bit resolution, and dual-channel simultaneous sampling means both channels share the same encode clock edge - critical for I/Q demodulation and phase-coherent measurements. Key features of the LTC2270IUP include 84.1 dB SNR, 99 dB SFDR, 2-channel simultaneous sampling at 20 Msps per channel, and an industrial temperature range of -40C to +85C. The 64-lead QFN (9x9 mm) package exposes a thermal pad for low thermal resistance, while differential inputs reject common-mode noise. The pipelined architecture provides low latency relative to sigma-delta ADCs of equivalent bandwidth. The LTC2270 is fabricated on a BiCMOS process optimized for high-speed sampling, supporting single 3V analog supply and 1.8V-3V digital supply. Internal reference and selectable input ranges simplify board design, while the LVDS or CMOS digital output interface (variant-dependent) integrates with FPGAs and ASICs. Optional dithering mode can be enabled to improve SFDR for small-signal or single-tone input scenarios. Typical applications include communications receivers (cellular base stations, software-defined radio), medical imaging (ultrasound beamformers), high-end instrumentation, and multi-channel data acquisition systems. The 84.1 dB SNR and 99 dB SFDR make it well suited to wide dynamic range signals. When designing with this part, pay close attention to analog input common-mode voltage and the driven front-end amplifier selection. The encode clock jitter directly limits SNR at high input frequencies - a low-jitter clock source is essential to preserve the datasheet's AC performance. This page synthesizes distributor pricing, drop-in alternatives from the LTC2208/LTC226x family, and practical design notes not consolidated in the manufacturer datasheet.
LTC2271CUKG - 16-Bit 20Msps Dual Serial ADC | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2271CUKG is a 16-bit, 20 Msps, dual-channel simultaneous-sampling pipelined ADC in a 52-pin QFN (7 mm x 8 mm) package. It delivers 84.1 dB SNR and 99 dB spurious-free dynamic range (SFDR) at the full 20 Msps conversion rate, with 2 independent serial LVDS outputs that simplify board routing. The device accepts single-ended analog inputs from a wide 1.7 V to 1.9 V common-mode range, allowing direct interface with a broad range of IF stages and baseband signal chains. A pipelined ADC is a high-speed analog-to-digital converter that processes analog samples through multiple cascaded low-resolution stages per clock cycle, achieving both high sampling rates and high resolution while keeping per-stage comparator accuracy requirements moderate. Pipelined ADCs occupy the middle ground between flash ADCs (fastest, lowest resolution) and successive-approximation ADCs (SAR, slowest, highest accuracy), making them the dominant architecture for communications, test instrumentation, and high-density imaging. Within the ADC taxonomy, the LTC2271 belongs to the pipelined -> high-speed -> dual-channel subfamily, well suited to multi-antenna receivers and I/Q signal processing. Key features of the LTC2271 include 84.1 dB SNR, 99 dB SFDR, internal dither for spurious-tone suppression, an internal clock duty-cycle stabilizer, and pin-selectable LVDS or CMOS output modes. The part dissipates approximately 230 mW per channel at 20 Msps and offers a low-power shutdown mode that drops consumption to microwatts for portable or duty-cycled applications. Its differential analog inputs yield 5 V p-p full-scale swing when used with a 1:4 transformer interface, providing strong immunity to common-mode noise and supply-induced artifacts. The architecture uses two matched sample-and-hold front-ends followed by 16-bit correction logic to guarantee no missing codes over the full -40 °C to +85 °C commercial temperature range. A 1.2 GHz input bandwidth and aperture delay matching between the two channels enable precise simultaneous acquisition - essential for diversity receivers, beamforming front-ends, and multi-axis instrumentation systems. Typical applications include cellular base-station receivers, cable-modem head-ends, multi-channel data-acquisition front-ends, software-defined radio (SDR), and high-end imaging systems such as medical ultrasound. The dual-channel simultaneous sampling also suits phase-sensitive industrial test equipment where channel-to-channel skew must remain under 30 ps. When using the LTC2271CUKG in a PCB layout, place the analog input RC network as close as possible to the AIN pins and route LVDS output pairs as matched 100 ohm differential traces. The exposed pad on the QFN-52 must be soldered to a continuous ground plane to provide both the low-impedance return path and thermal dissipation - inadequate pad soldering degrades SNR by 1-2 dB in practice. This page synthesizes pricing, drop-in pin-compatible alternatives, and PCB/layout design notes for the LTC2271CUKG that the manufacturer datasheet alone does not consolidate in one place.
LTC2271IUKG - 16-Bit 20Msps Dual ADC, 84.1dB SNR | Analog Devices
The Analog Devices LTC2271IUKG is a 16-bit, 20 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package. It integrates two ADC cores, each capable of 84.1 dB SNR and 99 dB spurious-free dynamic range (SFDR) at the full 20 Msps throughput, with selectable input ranges of 1 Vp-p to 2.1 Vp-p per channel. A serial SPI port is provided for per-channel configuration of input range, shutdown, and nap modes, and the LTC2271 is offered in industrial (IUKG) and commercial (CUKG) temperature grades. A pipelined ADC is a high-speed successive-stage architecture that processes one sample per clock cycle after an initial pipeline latency, enabling sample rates from tens to hundreds of Msps while maintaining 14- to 16-bit resolution. Pipelined ADCs are the workhorse converter class in communications infrastructure, defense radar, medical imaging front ends, and high-speed test and measurement - bridging the analog domain (sensors, IF stages) and the digital signal-processing domain (FPGA/ASIC baseband). The LTC2271 delivers 84.1 dB SNR and 99 dB SFDR at 20 Msps with low-latency CMOS outputs. Selectable 1 Vp-p or 2.1 Vp-p input ranges let the designer optimize SNR for transformer-coupled or single-ended front ends. Independent shutdown and nap modes reduce power dissipation when a channel is idle. The SPI configuration port eliminates external resistor-set biasing, simplifying multi-board factory calibration. The architecture is a fully differential switched-capacitor pipeline per channel, followed by proprietary digital post-processing that linearizes the transfer function. This internal calibration removes INL and DNL errors at power-up and tracks temperature drift, allowing the LTC2271 to deliver 16-bit performance without external trimming. The 52-pin QFN package has an exposed thermal pad tied to analog ground, providing low-inductance ground return and a thermal resistance of approximately 32 C/W. Typical applications include multi-channel cellular base-station receivers (MIMO 4G/5G digitizers), radar and sonar array digitization, IF sampling in software-defined radio, ultrasound beamforming front ends, and high-speed multichannel data-acquisition cards for automated test equipment. Designers choose the LTC2271 when 16-bit accuracy and 99 dB SFDR are required at sample rates below 25 Msps. When laying out the PCB, place the analog input traces as a 100-ohm differential microstrip with matched length, and bond the exposed pad (EP) directly to the analog ground plane through multiple thermal vias. Decouple AVDD and OVDD with 0.1 uF X7R capacitors as close as possible to each pin pair. Keep the encode clock (ENC+/ENC-) routing short and 100-ohm terminated to minimize aperture jitter. This page synthesizes distributor stock data, drop-in same-package alternatives, application-specific companion parts, and practical design notes not consolidated in the manufacturer datasheet alone.
LTC2272CUJ - 16-Bit 65Msps Serial Output ADC | Analog Devices
The Analog Devices LTC2272CUJ is a 16-bit, 65 Msps pipelined analog-to-digital converter with a JESD204-compliant serial output, housed in a 40-lead QFN (6x6 mm) package. The part features a 700 MHz input bandwidth, a programmable gain amplifier (PGA) front end, and a single differential input channel designed for digitizing high-frequency, wide-dynamic-range signals such as those found in communications, radar, and instrumentation front-ends. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time analog voltage or current into a discrete digital code proportional to the input magnitude. Within the broader signal-chain taxonomy, the LTC2272CUJ belongs to the high-speed pipelined ADC sub-family, which sits between successive-approximation-register (SAR) ADCs (typically <10 Msps) and flash or folding-interpolated ADCs (>250 Msps). Pipelined ADCs sample at rates from a few Msps up to several hundred Msps while delivering 12-16 bit resolution, making them the workhorse for software-defined radio, digital oscilloscopes, and base-station receivers. Key features include an input bandwidth of 700 MHz that supports IF undersampling architectures, a PGA that lets the user optimize the full-scale range for the signal at hand, an integrated clock duty-cycle stabilizer, and differential analog inputs optimized for driving the converter with an RF transformer or differential op-amp. The serialized LVDS output conforms to the JEDEC JESD204 specification, which drastically reduces the parallel bus pin count compared with traditional CMOS or LVDS parallel ADCs. The part is fabricated on a low-power CMOS process and includes an internal reference. Power is typically delivered from a single 1.8 V supply for the analog core and a separate 1.8 V supply for the digital LVDS output drivers, both of which can be sequenced independently to simplify power-up control. Typical applications include cellular base-station receivers, cable CMTS upstream paths, radar digitizers, and high-end digital oscilloscopes. The wide input bandwidth also makes the LTC2272CUJ useful for IF sampling in software-defined radio (SDR) platforms and for medical ultrasound beamforming front-ends. When designing with this converter, pay close attention to the analog input drive network - use a wideband transformer or differential amplifier and ensure the PCB layout provides controlled-impedance differential traces, a solid ground plane, and decoupling within a few millimeters of every supply pin to achieve the rated SNR and SFDR. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes that are not collected in the manufacturer datasheet.
LTC2272IUJ - 16-Bit 65Msps JESD204 Serial ADC | Analog Devices
The Analog Devices LTC2272IUJ is a 16-bit, 65 Msps analog-to-digital converter that serializes its output via a JESD204-compliant high-speed serial link, housed in a 40-pin 6x6 mm QFN (IUJ) package. The LTC2272IUJ operates from a single 1.8 V analog supply and a separate 1.8 V digital supply, drawing [DATA_NEEDED: current analog or supply] of core current while supporting an analog input bandwidth of 700 MHz suitable for undersampling and wideband IF digitization. A pipelined ADC (pipelined analog-to-digital converter) is a multi-stage converter architecture that achieves high sampling rates by cascading many low-resolution flash stages with sample-and-hold amplifiers between them; this family (LTC2273/LTC2272) targets demanding communications and instrumentation applications. Within the broader taxonomy, the LTC2272IUJ belongs to: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> integrated circuit. Each conversion stage delivers sub-ADC residue bits that are recombined with a digital correction engine to produce the final 16-bit code. Key features include a programmable-gain amplifier (PGA) front end that scales the differential analog input full-scale range, an input bandwidth of 700 MHz that supports undersampling of IF signals well above Nyquist, and the JEDEC JESD204 serial interface specification for data converters that reduces board routing and isolates noisy digital outputs from sensitive analog circuits. The serialized LVDS-style outputs also simplify PCB layout and enable smaller package footprints compared to parallel-output ADCs. Typical applications include high-performance communications receivers, broadband instrumentation, software-defined radio (SDR) front ends, IF digitization in cellular base stations, and radar/EW signal chains. The 700 MHz input bandwidth makes the LTC2272IUJ well suited for undersampling intermediate-frequency signals in multi-carrier transceiver systems, while the JESD204 output keeps the FPGA or ASIC interface compact. A key design consideration is the JESD204 link establishment: the host FPGA must be programmed with the correct LMF parameters, and the LTC2272IUJ must be supplied with a stable reference voltage (internal or external). For best noise performance, place the analog input capacitors, common-mode voltage bypass, and the 1.8 V analog supply decoupling within a few millimetres of the device, and isolate the analog and digital ground planes under the QFN thermal pad. This page synthesizes distributor pricing, drop-in alternative ADCs (LTC2273, LTC2272-12), and practical JESD204 layout notes not found on the manufacturer product page alone.
LTC2273IUJ - 16-Bit 80Msps Serial JESD204 ADC | Analog Devices
The Analog Devices LTC2273IUJ is a 16-bit, 80Msps analog-to-digital converter (ADC) with a high-speed JESD204 serial output interface, packaged in a 40-lead QFN (6x6 mm). It features 700 MHz analog input bandwidth, a programmable gain amplifier (PGA) front end, and serial output that follows the JEDEC JESD204 specification for data converters, eliminating parallel-data skew issues in high-density digital designs. An ADC (Analog-to-Digital Converter) is a semiconductor device that samples continuous analog voltage signals and converts them into discrete digital codes. High-speed pipelined ADCs like the LTC2273 sit between the analog front end (sensor, amplifier, filter) and the digital signal processor or FPGA, with sample rates from tens of megasamples per second to gigasamples per second. They are members of the data converter IC family within the broader signal chain hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. The 16-bit resolution provides 65536 discrete codes, enabling wide dynamic range capture. Key features include 80Msps sampling rate (65Msps for the pin-compatible LTC2272), 700 MHz input bandwidth for undersampling of IF signals, programmable input range via the PGA front end, JESD204 serial output for board-area reduction, and 40-lead QFN package. The PGA optimizes the input range for maximum SNR across diverse signal amplitudes. Operating from a 3.3V supply, the part dissipates approximately 1.4W during full-speed conversion and supports an industrial -40C to +85C temperature range. The pipelined architecture uses multi-stage switched-capacitor gain stages with digital error correction, achieving 77 dBFS SNR and 90 dBc SFDR at 30 MHz input. The JESD204 serial interface transmits data over 1 to 2 lanes at up to 3.2 Gbps per lane, providing deterministic latency and eliminating wide parallel data buses between the ADC and the FPGA/ASIC. The 700 MHz input bandwidth supports undersampling of IF frequencies, simplifying receiver architectures by eliminating a downconversion stage. Typical applications include cellular base-station receivers (LTE, WCDMA, GSM), software-defined radio (SDR), digital oscilloscopes, radar and lidar systems, medical imaging, and cable modems. The combination of high input bandwidth, JESD204 output, and 16-bit resolution is well suited to multi-carrier, multi-standard communications infrastructure where dynamic range and channel density matter. When designing with this part, provide a low-jitter clock source (<200 fs RMS) to preserve SNR at high input frequencies. Decouple AVDD and DVDD supplies separately with 10uF and 0.1uF ceramic capacitors placed within 5 mm of the supply pins. Route the JESD204 serial lanes as 100 ohm differential pairs, length-matched to within 5 mils, and keep them isolated from noisy digital returns. This page synthesizes the manufacturer datasheet, real distributor pricing, JESD204 pin-compatible alternatives from the LTC226x family, and practical PCB-layout notes not found on the manufacturer's product page, giving an engineer one consolidated reference for design-in.
LTC2274CUJ - 16-Bit 105Msps JESD204 Serial ADC | Analog Devices
The Analog Devices LTC2274CUJ is a 16-bit, 105 Msps analog-to-digital converter with a high-speed JESD204 serial interface, packaged in a 40-pin QFN (6x6 mm) with exposed pad. Designed for digitizing high-frequency, wide-dynamic-range signals, it offers an analog input bandwidth of 700 MHz and an optimized input range via an integrated PGA front end. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog waveforms and outputs discrete digital codes at a sample clock rate. The 16-bit resolution places the LTC2274 in the precision ADC tier, and a pipelined architecture typically delivers sustained high sample rates while keeping per-sample latency predictable. The LTC2274 specifically outputs its data via the JEDEC JESD204 serial interface, a serializer/link-layer standard that reduces board-routing congestion compared to parallel LVDS outputs. Key specifications include 16-bit resolution, 105 Msps sample rate, 700 MHz analog input bandwidth, 1 input channel, pipelined architecture, and a JESD204 serial output (replacing traditional CMOS/LVDS parallel buses). It is offered in the 40-QFN (6x6) package, lead-free (#PBF suffix), commercial temperature grade (-40C to +85C). Technically, the LTC2274 uses a multi-stage pipelined core with proprietary proprietary front-end PGA, allowing the input full-scale range to be scaled for optimum SNR vs. FSR tradeoffs. The JESD204 link supports deterministic latency and lane rates suitable for downstream FPGAs/ASICs, and the wide 700 MHz input bandwidth permits undersampling of IF/RF signals in communications systems. Typical applications include wideband communications, cellular base-station receiver IF digitizers, test and measurement instrumentation, medical imaging, defense electronics, and broadband data acquisition where JESD204 simplifies backplane routing to FPGAs. When designing the PCB, allocate a continuous ground plane under the exposed pad and stitch vias around the QFN perimeter to control switching currents from the JESD204 serializer. Decouple AVDD and DVDD rails with separate 1 uF/0.1 uF ceramic pairs, and route the JESD204 differential pairs with 100-ohm controlled impedance. This page synthesizes distributor pricing, JESD204-compatible pin-compatible alternatives, and PCB-layout guidance that complement - rather than duplicate - the manufacturer datasheet.
LTC2274IUJ - 16-Bit 105Msps Serial ADC, 40-QFN | Analog Devices
The Analog Devices LTC2274IUJ is a 16-bit, 105 Msps pipelined analog-to-digital converter with a high-speed serial (JESD204-style) output, housed in a 40-pin 6 mm × 6 mm QFN package. It is designed for digitizing high-frequency, wide-dynamic-range signals with an input bandwidth of 700 MHz and an SNR-optimized PGA front end that lets the user trade full-scale range against distortion performance. An ADC (analog-to-digital converter) is a data-converter subcategory of mixed-signal integrated circuits whose role is to sample continuous analog waveforms and produce discrete digital words at a defined sample rate. In the system hierarchy, the LTC2274IUJ sits between analog front-end signal conditioning (amplifiers, filters, transformers) and the FPGA/ASIC that consumes the digital data, placing it firmly inside the data-converter branch of the signal-chain taxonomy. Key features include 16-bit resolution at 105 Msps, 700 MHz analog input bandwidth, a programmable-gain amplifier (PGA) front end for input-range tuning, and a serialized LVDS output that minimizes pin count and simplifies PCB routing into modern FPGAs. The part shares a pin-compatible pinout across the LTC2272/LTC2273/LTC2274 family, allowing 65/80/105 Msps system scaling without PCB rework. Typical applications include basestation receivers, radar and lidar digitizers, high-end medical imaging, communications test equipment, and any wideband signal-chain that needs low-noise 16-bit conversion with a low-pin-count interface. The wide analog input bandwidth lets the same ADC digitize both baseband and IF signals after appropriate anti-alias filtering. When designing with this part, place the analog input network (transformer or driver amp) and the 40-QFN decoupling network as close as possible to the device. Use the PGA feature to optimize SFDR versus SNR for each end application, and ensure the LVDS serialization lanes are length-matched for clean FPGA capture. This page synthesizes verified distributor pricing, pin-compatible drop-in alternatives from the LTC227x family, and practical design notes not found in the manufacturer datasheet alone.
LTC2280CUP - Dual 10-Bit 105Msps Low-Noise 3V ADC | Analog Devices
The Analog Devices LTC2280CUP is a dual-channel, 10-bit, 105 Msps low-noise 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package. It integrates two matched pipelined ADC cores, supports simultaneous sampling on both channels, and operates from a single 3V supply (2.85V to 3.4V), drawing approximately 250 mW total. The pipelined architecture delivers 10-bit resolution at sample rates up to 105 Msps per channel, making it well suited to intermediate-frequency (IF) digitisation in communications receivers and to dual-channel imaging systems. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog signals and quantises them into discrete digital codes. Pipelined ADCs convert a single sample in multiple low-resolution stages, enabling high sampling rates at moderate power; within the broader taxonomy they belong to data-converter ICs, then data acquisition, then signal-chain semiconductors. The LTC2280CUP sits in the dual-channel, low-voltage, medium-resolution segment of this hierarchy. Key specifications include 61.6 dB signal-to-noise ratio (SNR) at 14 MHz input, 73 dB spurious-free dynamic range (SFDR), and an input-referred noise of 0.96 LSBrms. Each channel features its own track-and-hold amplifier, an internal reference, and a three-state digital output bus. Differential inputs are supported, and the device accepts both single-ended and differential drive topologies. Power-down, out-of-range, and data-ready indicators simplify system integration with FPGAs and DSPs. Typical applications include dual-channel digital oscilloscopes and data acquisition front-ends, IF sampling for software-defined radio (SDR) and cellular base stations, medical ultrasound beamforming arrays, and dual-stream CCD or CMOS imaging pipelines. The 3V analog supply and LVCMOS/LVDS-compatible outputs ease interface to modern low-voltage FPGAs and ASICs. When designing with this device, allocate generous ground and power planes around the 64-pin QFN exposed pad to manage thermal dissipation (about 1.2W at 105 Msps, dual channel). Use 0.1 uF ceramic bypass capacitors within 5 mm of every supply pin, and route the analog inputs as 50 ohm-controlled-impedance differential pairs to preserve SNR at the 70 MHz input bandwidth.