LTC2280CUP - Dual 10-Bit 105Msps Low-Noise 3V ADC | Analog Devices
MPN: LTC2280CUP ✓ نشطLTC2280CUP نظرة عامة
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog signals and quantises them into discrete digital codes. Pipelined ADCs convert a single sample in multiple low-resolution stages, enabling high sampling rates at moderate power; within the broader taxonomy they belong to data-converter ICs, then data acquisition, then signal-chain semiconductors. The LTC2280CUP sits in the dual-channel, low-voltage, medium-resolution segment of this hierarchy.
Key specifications include 61.6 dB signal-to-noise ratio (SNR) at 14 MHz input, 73 dB spurious-free dynamic range (SFDR), and an input-referred noise of 0.96 LSBrms. Each channel features its own track-and-hold amplifier, an internal reference, and a three-state digital output bus. Differential inputs are supported, and the device accepts both single-ended and differential drive topologies. Power-down, out-of-range, and data-ready indicators simplify system integration with FPGAs and DSPs.
Typical applications include dual-channel digital oscilloscopes and data acquisition front-ends, IF sampling for software-defined radio (SDR) and cellular base stations, medical ultrasound beamforming arrays, and dual-stream CCD or CMOS imaging pipelines. The 3V analog supply and LVCMOS/LVDS-compatible outputs ease interface to modern low-voltage FPGAs and ASICs.
When designing with this device, allocate generous ground and power planes around the 64-pin QFN exposed pad to manage thermal dissipation (about 1.2W at 105 Msps, dual channel). Use 0.1 uF ceramic bypass capacitors within 5 mm of every supply pin, and route the analog inputs as 50 ohm-controlled-impedance differential pairs to preserve SNR at the 70 MHz input bandwidth.
بدائل مباشرة لـ LTC2280CUP — نفس الحزمة، متوافق دبوس بدبوس. تُستثنى القطع ذات الحزم المختلفة التي تتطلب تعديل PCB.
الطرازات في هذه السلسلة
طرازات من نفس السلسلة متوافقة تمامًا مع LTC2280CUP (نفس عامل الشكل والبصمة) — يختلف في Package, SFDR, SNR, RoHS Status, Input Type.
LTC2280IUP
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منها📋 بديل مرجعي (غير موجود في الكتالوج)
LTC2221CUP
✅ بديل مباشرتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2155CUP-12
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منهاتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2150CUJ-14
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منهاتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2180CUP
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منهاتواصل لمعرفة السعر
عرض ورقة البيانات ←LTC2280CUP الحدود القصوى والخصائص الكهربائية
| الدقة | 10 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 105 Msps per channel |
| Architecture | Pipelined |
| Input Type | Differential / single-ended |
| Supply Voltage (Analog) | 3 V (2.85 V to 3.4 V) |
| Supply Voltage (Digital) | 3 V |
| Power Dissipation (typical) | 250 mW at 105 Msps, both channels |
| SNR (14 MHz input) | 61.6 dB |
| SFDR | 73 dB |
| Input-Referred Noise | 0.96 LSBrms |
| Input Bandwidth | 70 MHz |
| Output Format | LVCMOS (parallel) |
| نطاق درجة حرارة التشغيل | 0 C to +70 C (commercial grade) |
| العلبة | 64-pin QFN (9x9 mm) with exposed pad |
| حالة RoHS | Compliant (lead-free #PBF suffix) |
تكوين أطراف LTC2280CUP
| دبوس 1 | OGND — Output buffer ground reference |
| دبوس 2 | DVDD — 3V digital supply |
| دبوس 3 | D1B_0 — Channel B digital output bit 0 (LSB) |
| دبوس 4 | D1B_1 — Channel B digital output bit 1 |
| دبوس 5 | D1B_2 — Channel B digital output bit 2 |
| دبوس 6 | D1B_3 — Channel B digital output bit 3 |
| دبوس 7 | D1B_4 — Channel B digital output bit 4 |
| دبوس 8 | D1B_5 — Channel B digital output bit 5 |
| دبوس 9 | D1B_6 — Channel B digital output bit 6 |
| دبوس 10 | D1B_7 — Channel B digital output bit 7 |
| دبوس 11 | D1B_8 — Channel B digital output bit 8 |
| دبوس 12 | D1B_9 — Channel B digital output bit 9 (MSB) |
| دبوس 13 | OGND — Output buffer ground |
| دبوس 14 | OFB — Channel B out-of-range flag |
| دبوس 15 | OGND — Output buffer ground |
| دبوس 16 | DVDD — 3V digital supply |
| دبوس 17 | CLKOUTB — Channel B clock output (data ready) |
| دبوس 18 | OGND — Output buffer ground |
| دبوس 19 | CLKOUTA — Channel A clock output (data ready) |
| دبوس 20 | DVDD — 3V digital supply |
| دبوس 21 | OFA — Channel A out-of-range flag |
| دبوس 22 | OGND — Output buffer ground |
| دبوس 23 | D1A_0 — Channel A digital output bit 0 (LSB) |
| دبوس 24 | D1A_1 — Channel A digital output bit 1 |
| دبوس 25 | D1A_2 — Channel A digital output bit 2 |
| دبوس 26 | D1A_3 — Channel A digital output bit 3 |
| دبوس 27 | D1A_4 — Channel A digital output bit 4 |
| دبوس 28 | D1A_5 — Channel A digital output bit 5 |
| دبوس 29 | D1A_6 — Channel A digital output bit 6 |
| دبوس 30 | D1A_7 — Channel A digital output bit 7 |
| دبوس 31 | D1A_8 — Channel A digital output bit 8 |
| دبوس 32 | D1A_9 — Channel A digital output bit 9 (MSB) |
| دبوس 33 | OGND — Output buffer ground |
| دبوس 34 | DVDD — 3V digital supply |
| دبوس 35 | CLK — External clock input |
| دبوس 36 | OE — Output enable (active high) |
| دبوس 37 | SHDN — Power-down control (active high) |
| دبوس 38 | REFT — Internal reference top |
| دبوس 39 | REFB — Internal reference bottom |
| دبوس 40 | REFOUT — Internal reference output (1.5V typical) |
| دبوس 41 | SENSE — Reference programming pin |
| دبوس 42 | AGND — Analog ground reference |
| دبوس 43 | AVDD — 3V analog supply |
| دبوس 44 | VCM — Common-mode voltage output (1.5V) |
| دبوس 45 | AIN2+ — Channel 2 positive analog input |
| دبوس 46 | AIN2- — Channel 2 negative analog input |
| دبوس 47 | AGND — Analog ground |
| دبوس 48 | AVDD — 3V analog supply |
| دبوس 49 | AIN1+ — Channel 1 positive analog input |
| دبوس 50 | AIN1- — Channel 1 negative analog input |
| دبوس 51 | VCM — Common-mode voltage output |
| دبوس 52 | AVDD — 3V analog supply |
| دبوس 53 | AGND — Analog ground |
| دبوس 54 | AGND — Analog ground |
| دبوس 55 | AVDD — 3V analog supply |
| دبوس 56 | AGND — Analog ground |
| دبوس 57 | AVDD — 3V analog supply |
| دبوس 58 | AGND — Analog ground |
| دبوس 59 | AVDD — 3V analog supply |
| دبوس 60 | AGND — Analog ground |
| دبوس 61 | AVDD — 3V analog supply |
| دبوس 62 | AGND — Analog ground |
| دبوس 63 | DVDD — 3V digital supply |
| دبوس 64 | OGND — Output buffer ground |
التطبيقات النموذجية
LTC2280CUP مناسب لـ 6 التطبيقs: Dual-Channel IF Sampling for Software-Defined Radio, Medical Ultrasound Beamforming Front-End, Dual-Stream CCD/CMOS Image Acquisition, Communications Test and Measurement Instrumentation, Multi-Channel Data Acquisition Front-End, Radar and Lidar Baseband Digitisation.
Dual-Channel IF Sampling for Software-Defined Radio
The LTC2280CUP's dual-channel 105 Msps sampling and 70 MHz input bandwidth make it ideal for IF digitisation in software-defined radio receivers. Its 61.6 dB SNR at 14 MHz input preserves modulation accuracy on 64-QAM signals, while the matched dual channels allow I/Q baseband or diversity reception in a single IC. Place the ADC downstream of a 2-stage IF filter chain; supply 3V from a low-noise LDO like the LT3042 to avoid corrupting SNR. Unlike a discrete 2-ADC solution, the matched internal track-and-hold amplifiers eliminate gain and offset mismatches that would otherwise require per-channel calibration.
موصى به
Medical Ultrasound Beamforming Front-End
In ultrasound beamforming arrays, the LTC2280CUP simultaneously samples multiple receive channels at 105 Msps, enabling digital beamforming across a 32- or 64-element transducer array. The 73 dB SFDR rejects harmonic distortion from piezoelectric transducers, preserving image contrast, while the 10-bit resolution is sufficient for B-mode imaging where dynamic range is limited by the tissue interface. Mount the QFN-64 with a continuous copper ground plane under the exposed pad to dissipate 250 mW without thermal throttling. Per-channel digital outputs connect directly to an FPGA for delay-and-sum beamforming.
موصى به
Dual-Stream CCD/CMOS Image Acquisition
Industrial and scientific cameras use the LTC2280CUP to digitise two parallel image sensor streams at 105 Msps per channel, supporting up to 10K line-rate CCD sensors when pixel clocking exceeds 100 MHz. The dual channels enable simultaneous capture of red/blue or colour-stereo image pairs without external multiplexing, halving the FPGA pin count. The 64-pin QFN (9x9) package fits in space-constrained camera heads, and the 3V single supply aligns with modern CMOS sensor rails. Use matched-length routing on the parallel digital outputs to minimise channel-to-channel skew below one clock period.
موصى به
Communications Test and Measurement Instrumentation
The LTC2280CUP serves dual roles in test equipment: capturing wideband signals in a digitising oscilloscope channel, and providing a second matched channel for trigger/synchronisation paths. Its 61.6 dB SNR supports 10-bit ENOB measurement at 14 MHz, while 73 dB SFDR is adequate for spectral purity tests on RF stimuli. Per-channel power-down reduces consumption to <50 mW when only one channel is in use during calibration routines. Pair the ADC with an FPGA implementing a custom FFT engine; the parallel LVCMOS outputs eliminate the latency of serial LVDS interfaces used in higher-end parts.
موصى به
Multi-Channel Data Acquisition Front-End
Factory automation and process control systems use the LTC2280CUP as a dual-channel digitiser for vibration, acoustic, or strain-gauge signals sampled at 105 Msps. The simultaneous sampling eliminates phase skew between channels, critical for cross-correlation analysis in modal testing. With differential inputs, the ADC rejects 50/60 Hz line noise common in industrial environments, and the 3V single supply simplifies integration into PLC backplanes. Combined with a microcontroller or FPGA for FIR filtering, the LTC2280CUP delivers a compact, low-power data acquisition subsystem.
موصى به
Radar and Lidar Baseband Digitisation
Automotive radar and lidar baseband processors use the LTC2280CUP to digitise I and Q signals from the IF strip at up to 105 Msps, supporting bandwidths of 50 MHz or more for high-resolution ranging. The 73 dB SFDR preserves target discrimination across the radar dynamic range, while the matched dual channels keep I/Q gain and offset matched within the ADC itself. Operating from a single 3V supply, the ADC integrates into compact sensor modules where size and power are constrained. The exposed-pad QFN-64 package allows direct PCB thermal management with copper pours.
موصى به
ملخص المنتجات الموصى بها
بيانات مرجعية هندسية لـ LTC2280CUP — المقارنة وإرشادات التصميم ومعلومات الامتثال.
دليل الاختيار
المقارنة مع البدائل
| المعامل | هذا المنتج | LTC2280IUP | LTC2221CUP | LTC2155CUP-12 | LTC2150CUJ-14 | LTC2180CUP |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9) | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same |
| Resolution | 10 bit | 10 bit | 12 bit | 12 bit | 14 bit | 16 bit |
| Sample Rate | 105 Msps | 105 Msps | 135 Msps | 170 Msps | 105 Msps | 105 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Supply Voltage | 3V (2.85V-3.4V) | 3V (2.85V-3.4V) | 3V (2.85V-3.4V) | 3.5V | 3.5V | 3.5V |
| SNR (14 MHz input) | 61.6 dB | 61.6 dB | 67.5 dB | 68 dB | 72 dB | 76 dB |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
أبرز الفروقات
- True dual-channel simultaneous sampling in a single 64-QFN IC (مقابلLTC2221CUP)
- 10-bit resolution at 105 Msps with 73 dB SFDR (مقابلLTC2280IUP)
- Drop-in compatible with 12/14/16-bit upgrade path on same footprint (مقابلLTC2155CUP-12, LTC2150CUJ-14, LTC2180CUP)
ملاحظات التصميم
The 64-pin QFN package has a centre exposed thermal pad that MUST be soldered to a clean, unbroken analog ground plane to achieve specified thermal and electrical performance. Use an array of thermal vias (0.3 mm drill, 0.5 mm pitch) under the pad to spread heat to inner ground layers. Place 0.1 uF X7R ceramic bypass capacitors within 3 mm of every AVDD and DVDD pin, with a single 10 uF tantalum bulk capacitor near the analog supply entry point.
Do not route digital output traces (D1A_0..9, D1B_0..9, OFA, OFB) under the analog input pins or across the analog ground plane; this couples switching noise into the input and degrades SNR by 5-10 dB. Use matched-length routing within each channel group (length matching within 1 mm) to minimise channel-to-channel skew. Drive the CLK input with a low-jitter (< 5 ps RMS) source; CLK jitter directly degrades SNR according to SNR = 20*log10(1 / (2*pi*f_in*jitter)).
For optimal 73 dB SFDR performance, drive the analog inputs differentially using a transformer (e.g., Mini-Circuits ADT1-1WT) or a differential driver such as the LTC6409. Single-ended drive typically loses 5-8 dB of SFDR due to even-order distortion. Terminate the analog inputs with 100 ohm differential across AIN+ and AIN- to set the input impedance and avoid standing waves on the analog traces.
Estimated: at 105 Msps dual-channel operation, total power dissipation is approximately 250 mW. Derive the analog 3V supply from a low-noise LDO such as the LT3042 or LT1763 rather than the switching regulator directly; switching ripple on AVDD reduces SNR by 3-6 dB per 10 mV of ripple. Use separate analog and digital ground planes joined only at a single point beneath the exposed pad.
معلومات الامتثال
RoHS and lead-free compliance confirmed by the #PBF suffix on the Analog Devices part number; non-PBF variant is older lead-containing stock. Halogen-free per the LTC2280CUP material declaration on the Analog Devices product page.
