A3PE3000L-PQG208I vs A3PE3000L-PQ208 مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ A3PE3000L-PQG208I بواسطة Microchip Technology و A3PE3000L-PQ208 بواسطة Microchip Technology. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
Microchip Technology
A3PE3000L-PQG208I - ProASIC3L Flash FPGA 3M Gates | Microchip
A3PE3000L-PQG208I ✓ نشطMicrochip Technology
A3PE3000L-PQ208 - 3M Gate Low-Power Flash FPGA | Microchip
A3PE3000L-PQ208 ✓ نشطمقارنة المواصفات
| المعامل | A3PE3000L-PQG208I | A3PE3000L-PQ208 |
|---|---|---|
| العلامة التجارية | Microchip Technology | Microchip Technology |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | نشط | نشط |
| Family | ProASIC3L | ProASIC3L (ProASIC3EL) |
| System Gates | 3000000 | 3,000,000 |
| Total RAM Bits | 516096 | — |
| Number of I/O | 147 | — |
| Supply Voltage Range | 1.14 V to 1.575 V | — |
| Core Voltage | 1.2 V (low-power option), 1.2 V to 1.5 V range | 1.2 V |
| درجة حرارة التشغيل | -40C to +100C (TJ) | 0C to +70C |
| العلبة | 208-BFQFP (PQFP 28x28 mm) | 208-BFQFP (PQ208), 1.0 mm pitch |
| نوع التركيب | Surface Mount | Surface Mount |
| Technology | 130 nm flash process | — |
| Maximum Operating Frequency | 781.25 MHz | — |
| Configuration Memory | On-chip flash, single-chip (no external boot device) | — |
| Special Features | FlashFreeze technology, Power Driven Layout support | — |
| Moisture Sensitivity | MSL rated (Yes per distributor data) | — |
| Packaging | Tray, factory pack quantity 24 | Tray |
| حالة RoHS | Lead free (per Microchip/Mouser listing of family) | RoHS Non-Compliant (contains lead) |
| Height | 3.4 mm | — |
| Length x Width | 28 mm x 28 mm | — |
| Embedded SRAM | — | 504 kbits true dual-port |
| User I/Os (PQ208) | — | 147 |
| جهد التغذية | — | 1.5 V |
| Maximum Frequency | — | 781.25 MHz |
| Process Technology | — | 130 nm, 7-layer metal (6 copper) CMOS |
| Logic Family | — | CMOS |
| Program Type | — | Flash-based, In-System Programmable |
| Power-Up Behavior | — | Live At Power-Up Level 0 |
| Configuration | — | Single-chip solution (no external boot device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |