EP2A15F672C9N vs EP2A15F672C9 مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ EP2A15F672C9N بواسطة Intel و EP2A15F672C9 بواسطة Altera. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
مقارنة المواصفات
| المعامل | EP2A15F672C9N | EP2A15F672C9 |
|---|---|---|
| العلامة التجارية | Intel | Altera |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | NRND | Obsolete |
| Logic Family | APEX II (CMOS) | APEX II (CMOS) |
| Series | Altera APEX II (EP2A) | — |
| Logic Elements / Cells | 16,640 | — |
| Equivalent Gates | 600,000 | — |
| Maximum User I/O Pins | 492 | — |
| Propagation Delay | 1.94 ns | 1.94 ns |
| Internal Operating Frequency (max) | 379 MHz | — |
| Technology Process | 0.15 µm all-layer copper CMOS, up to 8 metal layers | — |
| Core Supply Voltage | 1.5 V | 1.5 V |
| العلبة | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine BGA) | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| درجة حرارة التشغيل | 0°C to +85°C (commercial grade) | 0 °C to 85 °C (commercial) |
| نوع التركيب | Surface Mount | — |
| مستوى MSL | 3 (per FC-FBGA moisture sensitivity, typical) | — |
| حالة RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Speed Grade | Up to 1 Gbps (LVDS) | — |
| Embedded Memory | Embedded dual-port RAM blocks | ESB dual-port RAM / FIFO |
| Special Blocks | CAM (Content-Addressable Memory), dedicated multipliers, PLLs | — |
| Speed Grade | C9 (fastest commercial grade in the APEX II speed-grade system) | — |
| Usable Gates | — | 600 K |
| Logic Elements | — | 16640 |
| Macrocells | — | 1664 |
| Maximum User I/Os | — | 492 |
| Process Technology | — | 0.15 µm all-layer copper (up to 8 metal layers) |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 379 MHz |
| High-Speed I/O Support | — | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Configuration Interface | — | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | — | On-chip PLLs for clock synthesis and deskew |
| Compliance | — | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |