EP2AGZ300FF35C4N vs EP2AGZ300FF35C4G مقارنة
مقارنة تفصيلية جنبًا إلى جنب لـ EP2AGZ300FF35C4N بواسطة Altera و EP2AGZ300FF35C4G بواسطة Intel. قارن المواصفات الرئيسية والمعلمات الكهربائية والتغليف وحالة دورة الحياة والأسعار والتوافر لتحديد أفضل مكوّن لمتطلبات تصميمك.
مقارنة المواصفات
| المعامل | EP2AGZ300FF35C4N | EP2AGZ300FF35C4G |
|---|---|---|
| العلامة التجارية | Altera | Intel |
| الفئة | FPGA & CPLD | FPGA & CPLD |
| حالة دورة الحياة | Obsolete | NRND |
| Series | Arria II GZ | — |
| Logic Elements | 298,000 | 300,000 |
| Logic Array Blocks (LABs) | 11,920 | — |
| Embedded Memory (bits) | 18,854,912 (~17.9 Mbit) | — |
| User I/O Count | 554 | — |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Process Technology | 40 nm | 40 nm TSMC |
| Core Voltage | 0.9 V | 0.85 V to 1.1 V |
| Package Type | 1152-BBGA, FCBGA (flip-chip) | — |
| Terminal Form | Ball | — |
| Package Code (JEDEC) | HBGA | — |
| Operating Temperature Grade | Commercial (C4 = 0C to +85C) | — |
| Configuration Memory | SRAM-based (volatile, requires boot device) | — |
| Transceivers | Multi-gigabit transceivers integrated | 12 channels |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks] | — |
| PLLs | [DATA_NEEDED: PLL count] | 8 (up to 4 per quadrant) |
| حالة RoHS | Compliant (per Besenchips / DigiKey listing) | Compliant |
| Lead-Free Status | Lead free (per Besenchips listing) | — |
| نوع التركيب | Surface Mount | — |
| Maximum Operating Frequency | 500 MHz | — |
| Family | — | Arria II GZ |
| Adaptive Logic Modules (ALMs) | — | 119,000 |
| Embedded Memory | — | 16,624 Kbit (M9K + M144K) |
| Embedded 18x18 Multipliers | — | 736 |
| User I/O Pins | — | 554 |
| Max Transceiver Data Rate | — | 6.375 Gbps (C4 speed grade) |
| العلبة | — | 1152-ball FineLine BGA (FBGA-1152), 35x35 mm |
| درجة حرارة التشغيل | — | 0°C to +85°C (commercial C4 grade) |
| Speed Grade | — | 4 |
| Global Clock Networks | — | 16 |
| PCIe Hard IP | — | PCIe Gen2 x4 |
| Hard Memory Controller | — | DDR3 up to 800 MHz |
| Configuration | — | Passive Serial, Fast Passive Parallel, JTAG |
| مستوى MSL | — | 3 (168 hours) |